KR970018571A - Capacitor Manufacturing Method of Semiconductor Memory Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Memory Device Download PDF

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Publication number
KR970018571A
KR970018571A KR1019950031081A KR19950031081A KR970018571A KR 970018571 A KR970018571 A KR 970018571A KR 1019950031081 A KR1019950031081 A KR 1019950031081A KR 19950031081 A KR19950031081 A KR 19950031081A KR 970018571 A KR970018571 A KR 970018571A
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KR
South Korea
Prior art keywords
capacitor
lower electrode
memory device
semiconductor memory
hsg
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KR1019950031081A
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Korean (ko)
Inventor
류차영
심세진
김영선
박영옥
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950031081A priority Critical patent/KR970018571A/en
Publication of KR970018571A publication Critical patent/KR970018571A/en

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Abstract

플라즈마 처리를 이용한 반도체장치의 캐패시터 제조방법을 개시한다. 본 발명은 하부전극의 표면적 증가를 도모한 HSG(Hemi-Spherical Grainde) 공정을 이용한 반도체 메모리 장치의 캐패시터를 제조하는 방법에 있어서, 상기 캐패시터의 하부전극 물질인 비정질 실리콘(amorphous-Si)의 전표면에 걸쳐 인위적인 손상(damage)를 주어 표면 Si의 결정화 온도를 낮춤으로써 캐패시터의 표면적 증가를 도모한 저온 HSG 공정을 이용한다.A method of manufacturing a capacitor of a semiconductor device using a plasma process is disclosed. The present invention relates to a method of manufacturing a capacitor of a semiconductor memory device using a Hemi-Spherical Grainde (HSG) process aimed at increasing the surface area of a lower electrode, wherein the entire surface of amorphous silicon (amorphous-Si) which is a lower electrode material of the capacitor is used. The low temperature HSG process is used to increase the surface area of the capacitor by artificially damaging the surface and lowering the crystallization temperature of the surface Si.

상기 하부전극의 표면에 인위적으로 손상(damage)을 주는 방법으로 10~500 와트의 Ar, H2, Cl2, HBr 및 CHF3중의 어느 하나의 가스를 사용하는 플라즈마 처리방법을 사용한다.As a method of artificially damaging the surface of the lower electrode, a plasma treatment method using any one of 10 to 500 watts of Ar, H 2 , Cl 2 , HBr, and CHF 3 is used.

Description

반도체 메모리장치의 커패시터 제조방법Capacitor Manufacturing Method of Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1(a)도 내지 제1(d)도는 본 발명의 제1실시예에 의한 하부전극의 표면적 증가방법을 순차적으로 도시한 공정단면도이다.1 (a) to 1 (d) are process cross-sectional views sequentially illustrating a method of increasing the surface area of a lower electrode according to the first embodiment of the present invention.

Claims (7)

하부전극의 표면적 증가를 도모한 HSG(Hemi-Spherical Grainde) 공정을 이용한 반도체 메모리 장치의 캐패시터를 제조하는 방법에 있어서, 상기 캐패시터의 하부전극인 물질인 비정질 실리콘(amorphous-Si)의 전표면에 걸쳐 인위적인 손상(damage)를 주어 표면 Si의 결정화 온도를 낮춤으로써 캐패시터의 표면적 증가를 도모한 저온 HSG 공정을 이용하는 것을 특징으로 하는 캐패시터 제조방법.In the method of manufacturing a capacitor of a semiconductor memory device using a Hemi-Spherical Grainde (HSG) process to increase the surface area of the lower electrode, the entire surface of amorphous silicon (amorphous-Si), which is a material of the lower electrode of the capacitor A method for producing a capacitor, characterized by using a low temperature HSG process that increases the surface area of a capacitor by lowering the crystallization temperature of the surface Si by artificially damaging it. 제1항에 있어서, 상기 하부전극의 표면에 인위적으로 손상(damage)을 주는 방법으로 플라즈마 처리를 사용하는 것을 특징으로 하는 캐패시터 제조방법.The method of claim 1, wherein the plasma treatment is performed by artificially damaging the surface of the lower electrode. 제2항에 있어서, 상기 플라즈마 처리는 소정시간 동안 10~500 와트의 파워로 수행하는 것을 특징으로 하는 캐패시터 제조방법.The method of claim 2, wherein the plasma treatment is performed at a power of 10 to 500 watts for a predetermined time. 제2항에 있어서, 상기 플라즈마 가스로는 Ar, H2, Cl2, HBr 및 CHF3중의 어느 하나를 사용하는 것을 특징으로 하느 캐패시터 제조방법.The method of claim 2, wherein the plasma gas is any one of Ar, H 2 , Cl 2 , HBr, and CHF 3 . 제1항에 있어서, 상기 하부전극으로 사용될 비정질 실리콘(amorphous-Si)의 두께는 100Å~10000Å의 범위를 갖는 것을 특징으로 하는 캐패시터 제조방법.The method of claim 1, wherein the thickness of amorphous silicon (Si) to be used as the lower electrode is in the range of 100 kPa to 10000 kPa. 제1항에 있어서, 상기 비정질실리콘(amorphous-Si)은 인, 비소, 및 붕소 중의 어느 하나의 불순물이 인시튜(in-situ) 도핑된 것을 사용하는 것을 특징으로 하는 캐패시터 제조방법.The method of claim 1, wherein the amorphous silicon is a doped in-situ doped with any one of phosphorus, arsenic, and boron. 제1항에 있어서, 상기 결정핵 생성(seeding)시, SiH4, Si2H6중의 어느 한 가스를 이용하는 것을 특징으로 하는 캐패시터 제조방법.The method of claim 1, wherein at least one of SiH 4 and Si 2 H 6 is used for seeding.
KR1019950031081A 1995-09-21 1995-09-21 Capacitor Manufacturing Method of Semiconductor Memory Device KR970018571A (en)

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KR1019950031081A KR970018571A (en) 1995-09-21 1995-09-21 Capacitor Manufacturing Method of Semiconductor Memory Device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100338848B1 (en) * 1998-02-03 2002-05-30 가네꼬 히사시 Fabrication method of semiconductor device with hsg configuration

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100338848B1 (en) * 1998-02-03 2002-05-30 가네꼬 히사시 Fabrication method of semiconductor device with hsg configuration

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