KR970018382A - Method of forming channel stopper of semiconductor device - Google Patents

Method of forming channel stopper of semiconductor device Download PDF

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KR970018382A
KR970018382A KR1019950032089A KR19950032089A KR970018382A KR 970018382 A KR970018382 A KR 970018382A KR 1019950032089 A KR1019950032089 A KR 1019950032089A KR 19950032089 A KR19950032089 A KR 19950032089A KR 970018382 A KR970018382 A KR 970018382A
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semiconductor substrate
oxide film
forming
film
nitride film
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KR1019950032089A
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Korean (ko)
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KR0170908B1 (en
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송태식
장세억
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체소자의 채널스토퍼 형성방법에 관한 것으로, N채널과 채널스토퍼 영역의 N/P접합 특성이 저하되지 않으면서 펀치스루우 현상을 개선하기 위하여, 붕소의 질화막에서의 이온투사범위가 산화막의 것보다 더 작다는 특성을 이용하여 필드산화막의 중앙 하부의 반도체기판에만 채널스토퍼영역을 형성한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a channel stopper of a semiconductor device. In order to improve the punch-through phenomenon without deteriorating the N / P bonding characteristics of the N-channel and the channel stopper region, the ion projection range of the boron nitride film is an oxide film. The channel stopper region is formed only in the semiconductor substrate below the center of the field oxide film by using the characteristic of smaller than.

Description

반도체 소자의 채털 스토퍼 형성방법Method of forming a channel stopper of semiconductor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4A도 내지 제4F도는 본 발명의 제1실시예에 의해 반도체소자의 채널스토퍼를 제조하는 단계를 도시한 단면도.4A to 4F are sectional views showing the steps of manufacturing the channel stopper of the semiconductor device according to the first embodiment of the present invention.

Claims (13)

반도체 기판 상에 p-well을 형성하고, 반도체기판의 상부를 열산화하여 패드산화막을 형성하는 단계와, 그 상부에 제1질화막을 증착하고, 소자분리용 마스크를 사용하여 상기 제1질화막과 패드산화막을 식각하여 패턴을 형성하는 단계와, 상기 제1질화막과 패드산화막의 측벽에 질화막스페이서를 형성하고, 노출된 반도체기판의 일정깊이를 식각하여 홈을 형성하는 단계와, 상기 홈 저부의 노출된 반도체기판 상부면을 산화시켜 필드산화막을 형성하는 단계와, 전체 구조의 상부에 증착하되, 반도체기판의 홈의 중앙 상측에 좁은 간격의 요부를 갖도록 제3질화막을 증착하는 단계와 채널스토퍼용 이온을 주입하여 필드산화막 중앙부 저부의 반도체기판에 태널스토퍼를 형성하는 단계와, 상기 제3질화막, 제1질화막, 질화막스페이서 및 패드산화막을 식각하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 채널스토퍼 형성방법.Forming a p-well on the semiconductor substrate, thermally oxidizing the upper portion of the semiconductor substrate to form a pad oxide film, depositing a first nitride layer thereon, and using the device isolation mask, using the first nitride layer and the pad. Etching the oxide film to form a pattern, forming a nitride film spacer on sidewalls of the first nitride film and the pad oxide film, etching a predetermined depth of the exposed semiconductor substrate to form a groove, and exposing the bottom of the groove. Oxidizing the upper surface of the semiconductor substrate to form a field oxide film; depositing the upper surface of the entire structure; Forming a tanner stopper on the semiconductor substrate at the bottom of the field oxide layer, and etching the third nitride film, the first nitride film, the nitride film spacer, and the pad oxide film. Method of a semiconductor device, characterized in that the channel stopper comprises the step formation. 제1항에 있어서, 상기 패드산화막이 50 내지 150Å 두께로 증착되는 것을 특징으로 하는 반도체소자의 채널스토퍼 형성방법.The method of claim 1, wherein the pad oxide film is deposited to a thickness of 50 to 150 kHz. 제1항에 있어서, 소자분리용 마스크를 사용하여 상기 제1질화막 패드산화막을 식각할 때, 식가폭이 0.20 내지 0.25㎛인 것을 특징으로 하는 반도체소자의 채널스토퍼 형성방법.The method of claim 1, wherein when the first nitride film pad oxide film is etched by using a device isolation mask, an etch width is 0.20 to 0.25 탆. 제1항에 있어서, 상기 제1질화막이 1500 내지 2500Å 두께로 증착되는 것을 특징으로 하는 반도체소자의 채널스토퍼 형성방법.The method of claim 1, wherein the first nitride film is deposited to a thickness of 1500 to 2500 kHz. 제1항에 있어서, 상기 제2질화막이 300 내지 600Å 두께로 증착되는 것을 특징으로 하는 반도체소자의 채널스토퍼 형성방법.The method of claim 1, wherein the second nitride film is deposited to a thickness of 300 to 600 kHz. 제1항에 있어서, 상기 홈을 형성할때, 반도체기판을 200 내지 600Å 정도 식각하는 것을 특징으로 하는 반도체소자의 채널스토퍼 형성방법.The method of claim 1, wherein when the groove is formed, the semiconductor substrate is etched by about 200 to 600 microseconds. 제1항에 있어서, 상기 필드산화막이 2500 내지 3500Å 두께로 증착되는 것을 특징으로 하는 반도체소자의 채널스토퍼 형성방법.The method of claim 1, wherein the field oxide film is deposited to a thickness of 2500 to 3500 microns. 제1항에 있어서, 상기 제3질화막이 200 내지 500Å 두께로 증착되는 것을 특징으로 하는 반도체소자의 채널스토퍼 형성방법.The method of claim 1, wherein the third nitride film is deposited to a thickness of 200 to 500 GPa. 제1항에 있어서, 상기 채널스토퍼 영역 형성시 이온주입에너지를 80 내지 100KeV로 하는 것을 특징으로 하는 반도체소자의 채널스토퍼 형성방법.The method of claim 1, wherein the ion implantation energy is 80 to 100 KeV when the channel stopper region is formed. 반도체기판상에 p-well을 형성하고, 반도체기판의 상부를 열산화하여 패드산화막을 형성하는 단계와, 그 상부에 제1질화막을 증착하고, 소자분리용 마스크를 사용하여 상기 제1절화막과 패드산화막의 측벽에 질화막스페이서를 형성하고, 노출된 반도체기판의 일정깊이를 식각하여 홈을 형성하는 단계와, 전체 구조의 상부에 증착하되, 반도체기판의 홈의 중앙 상측에 좁은 간격의 요부를 갖도록 제3질화막을 증착하는 단계와, 채널스토퍼용 이온을 주입하여 필드산화막 중앙부 저부의 반도체기판에 제1채널스토퍼를 형성하는 단계와, 채널스토퍼용 이온을 주입하여 상기 제1채널스토퍼 저부의 반도체기판에 제2채널스토퍼를 형성하는 단계와, 상기 제3질화막, 제1질화막, 질화막스페이서 및 패드산화막을 식각하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 채널스토퍼 형성방법.Forming a pad oxide film by forming a p-well on the semiconductor substrate, thermally oxidizing an upper portion of the semiconductor substrate, depositing a first nitride layer on the semiconductor substrate, and using the device isolation mask to form a p-well; Forming a nitride film spacer on the sidewall of the pad oxide film, etching a predetermined depth of the exposed semiconductor substrate to form a groove, and depositing it on the upper part of the entire structure, but having a narrow gap in the center of the groove of the semiconductor substrate. Depositing a third nitride film, implanting channel stopper ions to form a first channel stopper in a semiconductor substrate at the bottom of the field oxide film, and implanting channel stopper ions to implant a semiconductor substrate at the bottom of the first channel stopper And forming a second channel stopper on the substrate, and etching the third nitride film, the first nitride film, the nitride film spacer, and the pad oxide film. Channel stopper formation method of the conductor elements. 제10항에 있어서, 상기 1차 이온주입에너지와 2차 이온주입에너지 차이가 10 내지 30KeV인 것을 특징으로 하는 반도체소자의 채널스토퍼 형성방법.The method of claim 10, wherein the difference between the primary ion implantation energy and the secondary ion implantation energy is 10 to 30 KeV. 반도체기판상에 p-well을 형성하고, 반도체기판의 상부를 열산화하여 패드산화막을 형성하는 단계와, 그 상부에 제1질화막을 증착하고, 소자분리용 마스크를 사용하여 상기 제1질화막과 패드산화막을 식각하여 패턴을 형성하는 단계와, 상기 제1질화막과 패드산화막의 측벽에 질화막스페이서를 형성하는 단계와, 노출된 반도체기판 상부면을 산화시켜 필드산화막을 형성하는 단계와, 전체 구조의 상부에 제3질화막을 증착하는 단계와, 채널스토퍼용 이온을 주입하여 필드산화막 중앙부 저부의 반도체기판에 채널스토퍼를 형성하는 단계와, 상기 제3질화막, 제1질화막, 질화막스페이서 및 패드산화막을 식각하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 채널스토퍼 형성방법.Forming a pad oxide film by forming a p-well on the semiconductor substrate, thermally oxidizing an upper portion of the semiconductor substrate, depositing a first nitride layer thereon, and using the device isolation mask, using the first nitride layer and the pad. Etching a oxide film to form a pattern, forming a nitride film spacer on sidewalls of the first nitride film and the pad oxide film, oxidizing an exposed upper surface of the semiconductor substrate to form a field oxide film, and forming an upper portion of the entire structure Depositing a third nitride film on the semiconductor substrate; forming a channel stopper on the semiconductor substrate at the bottom of the field oxide film by implanting ions for the channel stopper; and etching the third nitride film, the first nitride film, the nitride spacer, and the pad oxide film. A channel stopper forming method of a semiconductor device comprising a step. 반도체기판상에 p-well을 형성하고, 반도체기판의 상부를 열산화하여 패드산화막을 형성하는 단계와, 그 상부에 폴리실리콘층과 제1질화막을 증착하고, 소자분리용 마스크를 사용하여 상기 제1질화막, 폴리실리콘층 및 패드산화막을 식각하여 패턴을 형성하는 단계와, 노출된 반도체기판의 일정깊이를 식각하여 홈을 형성하는 단계와, 상기 홈 저부의 노출된 반도체기판 상부면을 산화시켜 필드산화막을 형성하는 단계와, 전체 구조의 상부에 제3질화막을 증착하는 단계와, 채널스토퍼용 이온을 주입하여 필드산화막 중앙부 저부의 반도체기판에 채널스토퍼를 형성하는 단계와, 상기 제3절화막, 제1절화막, 절화막스페이서, 폴리실리콘층 및 패드산화막을 식각하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 채널스토퍼 형성방법.Forming a p-well on the semiconductor substrate, thermally oxidizing the upper portion of the semiconductor substrate to form a pad oxide layer, depositing a polysilicon layer and a first nitride layer thereon, and using a device isolation mask. (1) forming a pattern by etching the nitride film, the polysilicon layer, and the pad oxide film; forming a groove by etching a predetermined depth of the exposed semiconductor substrate; and oxidizing the exposed upper surface of the semiconductor substrate at the bottom of the groove. Forming an oxide film, depositing a third nitride film on top of the entire structure, implanting channel stopper ions to form a channel stopper on the semiconductor substrate at the bottom of the field oxide film, the third cut film, And etching the first cut film, the cut film spacer, the polysilicon layer, and the pad oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950032089A 1995-09-27 1995-09-27 Channel stopper forming method of semiconductor device KR0170908B1 (en)

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