KR970018148A - Manufacturing method of fine pattern of semiconductor device - Google Patents
Manufacturing method of fine pattern of semiconductor device Download PDFInfo
- Publication number
- KR970018148A KR970018148A KR1019950031464A KR19950031464A KR970018148A KR 970018148 A KR970018148 A KR 970018148A KR 1019950031464 A KR1019950031464 A KR 1019950031464A KR 19950031464 A KR19950031464 A KR 19950031464A KR 970018148 A KR970018148 A KR 970018148A
- Authority
- KR
- South Korea
- Prior art keywords
- pattern
- photoresist pattern
- layer
- sog layer
- etched
- Prior art date
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- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
본 발명은 반도체소자의 미세패턴 제조방법에 관한 것으로서, 피식각층상에 충분한 폭의 라인을 갖는 감광막 패턴을 형성하고 상기 구조의 전표면에 SOG층을 형성한 후, 상기 SOG층의 상부를 CMP 방법으로 제거하여 감광막패턴의 상부를 노출시킨 후, 상기 노출된 감광막패턴을 산소 플라즈마로 제거하여 SOG층 패턴을 형성하고, 이를 마스크로 피식각층을 식각하여 피식각층 패턴을 형성하였으므로, 감광막패턴의 라인을 충분한 폭을 갖도록 형성하므로 상이 반전된 SOG층 패턴의 경우에는 미세한 폭의 라인이 형성되므로 공정이 간단하고, 안정되게 미세한 라인을 형성하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a micropattern of a semiconductor device, wherein a photoresist pattern having a sufficient width line is formed on an etched layer, and an SOG layer is formed on the entire surface of the structure, and then an upper part of the SOG layer is formed on a CMP method. After removing the photoresist pattern by exposing the upper portion of the photoresist pattern, the exposed photoresist pattern was removed with oxygen plasma to form an SOG layer pattern, and the etched layer was etched using a mask to form an etched layer pattern. Since the SOG layer pattern in which the phase is inverted is formed to have a sufficient width, a line having a fine width is formed, thereby simplifying the process and stably forming a fine line, thereby improving process yield and device operation reliability.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1A도 내지 제1E도는 본 발명에 따른 반도체소자의 미세패턴 제조 공정도.1A to 1E are fine pattern manufacturing process diagrams of a semiconductor device according to the present invention.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950031464A KR970018148A (en) | 1995-09-22 | 1995-09-22 | Manufacturing method of fine pattern of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950031464A KR970018148A (en) | 1995-09-22 | 1995-09-22 | Manufacturing method of fine pattern of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970018148A true KR970018148A (en) | 1997-04-30 |
Family
ID=66615881
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950031464A KR970018148A (en) | 1995-09-22 | 1995-09-22 | Manufacturing method of fine pattern of semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970018148A (en) |
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1995
- 1995-09-22 KR KR1019950031464A patent/KR970018148A/en not_active Application Discontinuation
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Legal Events
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WITN | Withdrawal due to no request for examination |