KR970017595A - Arrangement method of reference voltage generating circuit in semiconductor memory device - Google Patents

Arrangement method of reference voltage generating circuit in semiconductor memory device Download PDF

Info

Publication number
KR970017595A
KR970017595A KR1019950030743A KR19950030743A KR970017595A KR 970017595 A KR970017595 A KR 970017595A KR 1019950030743 A KR1019950030743 A KR 1019950030743A KR 19950030743 A KR19950030743 A KR 19950030743A KR 970017595 A KR970017595 A KR 970017595A
Authority
KR
South Korea
Prior art keywords
string
memory
word lines
reference voltage
semiconductor memory
Prior art date
Application number
KR1019950030743A
Other languages
Korean (ko)
Other versions
KR0167684B1 (en
Inventor
고영위
이형곤
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950030743A priority Critical patent/KR0167684B1/en
Publication of KR970017595A publication Critical patent/KR970017595A/en
Application granted granted Critical
Publication of KR0167684B1 publication Critical patent/KR0167684B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체 메모리 장치의 배치방법Arrangement method of semiconductor memory device

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

교류 응답 타임이 고속화 되어지는 메모리의 배치방법을 제공한다.Provides a method of arranging a memory in which the AC response time is increased.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

복수의 비트라인과 복수의 워드라인을 가지며, 단위 메모리 셀이 모여 하나의 메모리 스트링이 만들어 지며, 다수의 단위 메모리 셀로 이루어진 하나의 메모리 스트링이 비트 라인과 워드라인이 만나는 곳에 형성되며, 외부 어드레스 신호에 의해 메모리 스트링이 선택되는 구조를 가지는 메모리의 배치 방법은 선택된 로우 디코더에 의하여 동작하는 스트링 선택라인의 신호가 노말 어레이의 스트링과, 기준전압 발생회로부의 더미 스트링을 동시에 선택하는 구조로 배치함을 특징으로 한다.It has a plurality of bit lines and a plurality of word lines, unit memory cells are gathered to form a memory string, and a memory string consisting of a plurality of unit memory cells is formed where bit lines and word lines meet, and an external address signal. In the memory layout method having a structure in which the memory string is selected by the memory array, the signal of the string selection line operated by the selected row decoder is arranged so that the string of the normal array and the dummy string of the reference voltage generator circuit are simultaneously selected. It features.

4. 발명의 중요한 용도4. Important uses of the invention

비 휘발성 반도체 메모리의 기준셀 배치에 적합하게 사용된다.It is suitably used for the reference cell arrangement of the nonvolatile semiconductor memory.

Description

반도체 메모리 소자내의 기준전압 발생회로의 배치 방법Arrangement method of reference voltage generating circuit in semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 로우 디코더 및 메모리 셀 어레이간의 관계를 설명하기 위한 회로도,2 is a circuit diagram illustrating a relationship between a row decoder and a memory cell array according to the present invention;

제3도는 본 발명에 따른 메모리 셀 어레이중의 더미 셀 어레이의 배치를 보여주는 도면.3 shows a layout of a dummy cell array in a memory cell array in accordance with the present invention.

Claims (3)

복수의 비트라인과 복수의 워드라인을 가지며, 단위 메모리 셀이 모여 하나의 메모리 스트링이 만들어지며, 다수의 단위 메모리 셀로 이루어진 하나의 메모리 스트링이 비트 라인과 워드라인이 만나는 곳에 형성되며, 외부 어드레스 신호에 의해 메모리 스트링이 선택되는 구조를 가지는 메모리의 배치 방법에 있어서, 선택된 로우 디코더에 의하여 동작하는 스트링 선택라인의 신호가 노말 어레이의 스트링과, 기준전압 발생회로부의 더미 스트링을 동시에 선택하는 구조로 배치함을 특징으로 하는 방법.It has a plurality of bit lines and a plurality of word lines, unit memory cells are gathered to form a memory string, and a memory string consisting of a plurality of unit memory cells is formed where bit lines and word lines meet, and an external address signal. A method of arranging a memory having a structure in which a memory string is selected by the method, wherein the signal of the string selection line operated by the selected row decoder is arranged in such a manner that the string of the normal array and the dummy string of the reference voltage generation circuit part are simultaneously selected. Characterized in that. 제1항에 있어서, 상기 스트링 라인은 공유되나, 상기 워드라인들은 각기 분리되어 더미 스트링의 전압 레벨을 조절할 수 있게 한 것을 특징으로 하는 방법.The method of claim 1, wherein the string lines are shared, but the word lines are separated so as to adjust a voltage level of the dummy string. 제1항에 있어서, 더미 스트링의 갯수가 센스 앰프의 갯수와 같거나 작은 것임을 특징으로 하는 방법.The method of claim 1, wherein the number of dummy strings is less than or equal to the number of sense amplifiers. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950030743A 1995-09-19 1995-09-19 Layout method of standard voltage occurrence circuit in the semiconductor memory device KR0167684B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950030743A KR0167684B1 (en) 1995-09-19 1995-09-19 Layout method of standard voltage occurrence circuit in the semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950030743A KR0167684B1 (en) 1995-09-19 1995-09-19 Layout method of standard voltage occurrence circuit in the semiconductor memory device

Publications (2)

Publication Number Publication Date
KR970017595A true KR970017595A (en) 1997-04-30
KR0167684B1 KR0167684B1 (en) 1999-02-01

Family

ID=19427247

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950030743A KR0167684B1 (en) 1995-09-19 1995-09-19 Layout method of standard voltage occurrence circuit in the semiconductor memory device

Country Status (1)

Country Link
KR (1) KR0167684B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100507687B1 (en) * 1998-12-30 2005-10-26 주식회사 하이닉스반도체 Flash memory device and sensing method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100729365B1 (en) * 2006-05-19 2007-06-15 삼성전자주식회사 Flash memory device capable of preventing read fail due to dummy strings

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100507687B1 (en) * 1998-12-30 2005-10-26 주식회사 하이닉스반도체 Flash memory device and sensing method thereof

Also Published As

Publication number Publication date
KR0167684B1 (en) 1999-02-01

Similar Documents

Publication Publication Date Title
KR970003252A (en) Voltage sensing method of nonvolatile semiconductor memory
KR920018759A (en) Word Line Driver Circuits in Semiconductor Memory Devices
KR900005451A (en) Semiconductor memory device
KR970051182A (en) Semiconductor memory
KR900019028A (en) Semiconductor Memory Device with Redundant Block
KR910003670A (en) Static Semiconductor Memory
KR840003146A (en) Dynamic RAM Integrated Circuit Devices
KR860003603A (en) Semiconductor memory
KR930005015A (en) Semiconductor memory
KR930005025A (en) Semiconductor memory device with low power block selection
KR880009376A (en) Semiconductor memory
KR930011242A (en) Static memory
KR930018588A (en) Nonvolatile Semiconductor Memory Device
KR910013285A (en) Nonvolatile Semiconductor Memory
KR960042367A (en) Memory cell access method and access circuit of memory device
KR920006974A (en) Dynamic Semiconductor Memory Device
KR920010905A (en) Dynamic Random Access Memory Device with Improved Playback
KR930008850A (en) Semiconductor memory device with partitioned read data bus system
KR900002305A (en) Semiconductor memory
KR910010524A (en) Nonvolatile Semiconductor Memory
KR970017595A (en) Arrangement method of reference voltage generating circuit in semiconductor memory device
KR930005036A (en) Redundant cell array arrangement method of semiconductor memory device
KR880014569A (en) Semiconductor memory
KR960043244A (en) Layout method of nonvolatile memory device
KR930014607A (en) Stacktack Random Access Memory Device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060830

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee