KR960043244A - Layout method of nonvolatile memory device - Google Patents

Layout method of nonvolatile memory device Download PDF

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Publication number
KR960043244A
KR960043244A KR1019950013271A KR19950013271A KR960043244A KR 960043244 A KR960043244 A KR 960043244A KR 1019950013271 A KR1019950013271 A KR 1019950013271A KR 19950013271 A KR19950013271 A KR 19950013271A KR 960043244 A KR960043244 A KR 960043244A
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KR
South Korea
Prior art keywords
word lines
width
memory device
layout method
cell current
Prior art date
Application number
KR1019950013271A
Other languages
Korean (ko)
Other versions
KR0145854B1 (en
Inventor
김형복
류영균
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950013271A priority Critical patent/KR0145854B1/en
Publication of KR960043244A publication Critical patent/KR960043244A/en
Application granted granted Critical
Publication of KR0145854B1 publication Critical patent/KR0145854B1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM

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  • Read Only Memory (AREA)

Abstract

1. 청구범위에 기재된 발명이 속하는 기술 분야1. TECHNICAL FIELD OF THE INVENTION

난드형의 셀 구조와 감지증폭기를 가지는 불휘발성 메모리의 셀 전류를증대 시킬 수 있는 방법에 관한 것이다.The present invention relates to a method of increasing the cell current of a nonvolatile memory having a NAND-type cell structure and a sense amplifier.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

비트라인과 접지간의 저항을 최소화하여 셀 전류를 증대시키는 레이아웃 방법을 제공함에 있다.The present invention provides a layout method for increasing cell current by minimizing resistance between a bit line and ground.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

저장용 트랜지스터를 가지는 다수개의 워드라인들중 소정수의 상기 워드라인들의 폭을 동일하게 형성하고, 접지전압으로 이어진 그 나머지의 워드라인들의 폭은 상기의 폭 보다 작게 형성하는 것을 요지로 한다.The width of a predetermined number of word lines among the plurality of word lines having a storage transistor is equally formed, and the width of the remaining word lines leading to the ground voltage is smaller than the width.

4. 발명의 중요한 용도4. Important uses of the invention

셀 전류가 증대한 불휘발성 반도체 메모리 장치에 접합하게 사용된다.It is used to join a nonvolatile semiconductor memory device having an increased cell current.

Description

불휘발성 메모리 장치의 레이아웃 방법Layout method of nonvolatile memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 실시예에 따른 마스크 롬의 평면도.3 is a plan view of a mask ROM in accordance with an embodiment of the present invention.

Claims (2)

감지증폭부에 연결된 비트라인과, 상기 비트라인과 접지전압에 연결된 제1, 2 스트링을 선택하는 선택트랜지스터를 가지는 선택워드라인들과 데이타 내용이 기록되는 저장용 트랜지스터를 가지는 다수개의 워드라인들이 직렬로접속된 불휘발성 반도체 메모리 장치의 레이아웃 방법에 있어서 : 상기 저장용 트랜지스터를 가지는 다수개의 워드라인들중 소정수의 상기 워드라인들의 폭을 동일하게 형성하고, 접지전압으로 이어진 그 나머지의 워드라인들의 폭은 상기의폭보다 작게 형성하는 것은 특징으로 하는 불휘발성 반도체 메모리 장치의 레이아웃 방법.A plurality of word lines having a bit line connected to the sense amplifier, select word lines having a selection transistor for selecting first and second strings connected to the bit line and ground voltage, and a storage transistor in which data contents are written; A layout method of a nonvolatile semiconductor memory device connected to a semiconductor device, the method comprising: forming the same width of a predetermined number of word lines among a plurality of word lines having the storage transistor, The width of the nonvolatile semiconductor memory device, characterized in that to form smaller than the width. 제1항에 있어서; 상기 폭이 적게 형성된 워드라인들의 소정수는 임의 대로 정하는 것을 특징으로 하는 불휘발성 반도체 메모리 장치의 레이아웃 방법.The method of claim 1; And a predetermined number of word lines having a smaller width are arbitrarily determined. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950013271A 1995-05-25 1995-05-25 Method of layout for non-volatile memory device KR0145854B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950013271A KR0145854B1 (en) 1995-05-25 1995-05-25 Method of layout for non-volatile memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950013271A KR0145854B1 (en) 1995-05-25 1995-05-25 Method of layout for non-volatile memory device

Publications (2)

Publication Number Publication Date
KR960043244A true KR960043244A (en) 1996-12-23
KR0145854B1 KR0145854B1 (en) 1998-08-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950013271A KR0145854B1 (en) 1995-05-25 1995-05-25 Method of layout for non-volatile memory device

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Country Link
KR (1) KR0145854B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980005033A (en) * 1996-06-27 1998-03-30 김주용 Mask ROM device
KR20030060313A (en) * 2002-01-08 2003-07-16 삼성전자주식회사 Nand-type flash memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980005033A (en) * 1996-06-27 1998-03-30 김주용 Mask ROM device
KR20030060313A (en) * 2002-01-08 2003-07-16 삼성전자주식회사 Nand-type flash memory device

Also Published As

Publication number Publication date
KR0145854B1 (en) 1998-08-01

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