KR0167684B1 - Layout method of standard voltage occurrence circuit in the semiconductor memory device - Google Patents

Abstract

1. the technical field to which the invention described in the claims belongs; Arrangement method of semiconductor memory device

2. The technical problem to be solved by the invention; Provides a method of arranging a memory in which the AC response time is increased.

3. Summary of the Solution of the Invention; It has a plurality of bit lines and a plurality of word lines, unit memory cells are gathered to form a memory string, and a memory string consisting of a plurality of unit memory cells is formed where bit lines and word lines meet, and an external address signal. In the memory layout method having a structure in which the memory string is selected by the memory array, the signal of the string selection line operated by the selected row decoder is arranged so that the string of the normal array and the dummy string of the reference voltage generator circuit are simultaneously selected. It features.

4. Significant use of the invention; It is suitably used for the reference cell arrangement of the nonvolatile semiconductor memory.

Description

Arrangement method of reference voltage generating circuit in semiconductor memory device

1 shows a prior art memory cell array.

2 is a circuit diagram for explaining a relationship between a row decoder and a memory cell array according to the present invention.

3 shows a layout of a dummy cell array in a memory cell array in accordance with the present invention.

The present invention relates to a dummy cell arrangement method for generating a reference voltage in a memory cell array of a nonvolatile semiconductor device.

In general, a typical dummy cell structure used in a semiconductor device such as EEPRom is a form of NAND borrowing, in which the normal cell has the same structure. The reason is that the normal cell has the same structure as the normal cell, so that the same design rules as the normal cell can be applied to the dummy cell in the manufacturing process, and the reason is that the dummy cell can have the same proportional rate as the normal cell.

There are two types of semiconductor memory devices: a NOR type in which transistors are connected in parallel, and a transistor in series NAND type. In general, the NOR type is suitable for high-speed operation due to the large cell current, but has a limitation in large capacity due to the large cell size. However, the NOR type has a disadvantage of slower operation speed due to the smaller cell current than the NAND type. Therefore, it can be seen that a memory cell structure made of NAND among these two types has an advantage of reducing the area of the memory cell array. Here, an NAND type cell will be described as an example.

In general NAND type memory cells, a unit cell composed of poly and active self-alignment is composed of one transistor, and a plurality of cell transistors and two string select transistors constitute one unit memory string, and the unit memory string One end of is connected to the bit line and the other end is connected to ground. However, at this time, the ground is not connected to the metal, but is connected to the active, because the active and the metal connected to the ground must be made by the compact hole to be connected to each other, there is a problem that the layout area becomes large. Two unit memory strings are connected to one bit line contact hole, and this is repeatedly connected to the bit line, and a plurality of unit bit lines form a memory cell array. Strictly speaking, however, a memory cell array is a collection of cell blocks in which a number of unit bit lines are gathered by a certain number. The reason why a cell block is needed is that the ground of the memory string is connected to active as described above. If the memory string is repeatedly arranged repeatedly, the ground resistance becomes large, so that it must be connected to a material having good conductivity after being repeated for a certain number of times. At this time, the ground metal is formed in the column direction like the bit line, and space between the bit line and the ground line (Metal and Metal) is required according to the design rule of the process, and there must be a contact hole. This is why cell blocks are needed.

On the other hand, the recent rapid development of semiconductor memory devices has resulted in high density and high integration of integrated circuits, but the continuous reduction of design rules carried out to increase the density has made it impossible to ignore various process problems that could be ignored in the past. Many problems have arisen in cells that use the smallest possible line width in the process. One of them is the reduction in the effective width of the transistors due to Bird's Back. In the MOSN transistor, an insulating thick oxide film, called field oxide, is grown on the silicon substrate to prevent short-circuit by an electric field during process diffusion or chip operation. The field oxide is formed by the affinity between the oxide and silicon. As it grows up, it penetrates and grows into the inside of the substrate to form a pointed oval shape with the horizontal side as a whole. The pointed part of the tip is called a new part. If this part penetrates into the channel in the direction of the transistor, the part is not properly controlled by the gate of the transistor, and thus the width is reduced.

In the memory cell array, as the size of the active width and the space between neighboring actives become narrower with respect to the chip size, the effect of the loading effect in the photo / etch process becomes increasingly serious. In this loading effect, light passing through a small pattern in the process modifies the shape of the neighboring pattern due to diffraction and scattering phenomena, and more etching is performed when photo / etching in the non-dense area than in the area where the pattern is dense. The smaller the pattern, the greater the effect of the loading effect, which reduces the process margin, causing the chip to malfunction even with small process errors.

In other words, the active width of transistors caused by Bird's Beak is reduced during the active process. The solution is to solve the problem because almost all active patterns in the memory cell array are arranged to maintain a constant line width. By considering the effect width of the transistor in advance, if the active pattern is larger than the actual size or the oversize method is used, the problem of reducing the width of the transistor due to Buzz big can be sufficiently controlled. However, the memory cell array needs a space for supplying the ground voltage between the cell block and the cell block, and an oxide layer of this portion is formed between the memory cell string (Active) and the memory cell string (Active) that are uniformly arranged inside the block. As it has a wider width than the oxide film located at, the buzz big becomes relatively larger and thus smaller than the originally designed active width, resulting in a decrease in cell current and failure compared to other transistors that maintain a constant pattern. This is likely to occur. In order to solve this problem, there is a method of making the active width adjacent to the wide oxide film wider than other constant active widths or adding a dummy active pattern.

What has been described so far has been about the loading effect effect and resolution by Buzz Big in the memory cell array due to the high integration and high density of semiconductor devices.

1 is a diagram illustrating a conventional memory cell array and a row decoder configuration manufactured by the above-described method. In the NAND type cell memory, one memory cell transistor is connected to a memory cell transistor block 3 and a sense amplifier 5 is connected during read operation. It has a structure in which one data is read in a block. Here, each cell is selected by a word line driven by row decoder 1 and connected to a gate of a memory cell transistor, and each block shows a structure in which a dummy bit line is connected to a sense amplifier. Here, the dummy bit line is made to be used for loading like the bit line, and the dummy cell adjusts the channel length to be half of the bit line string current.

However, in the structure of FIG. 1, since the dummy cell 10, which is the reference voltage generating circuit, is not located in the cell array 3, but is located above or below the edge of the cell array in the layout of the chip, there is a concern that the above-described loading effect may increase. When selected, the resistance of the bit line and the resistance of the dummy bit line have been problematic, in terms of alternating current (AC) response time.

Accordingly, an object of the present invention is to provide a method of arranging a memory cell array which is suitable for high speed in a memory device and whose AC response time is improved.

Referring to the description of the operation of the row decoder 200 in FIG. 2, an external input signal is input to the predecoder of P and Q, respectively, and Pi and Qi selected by the predecoder are input to Low (GND). In the circuit diagram, the node A, which is the NOR gate NOR1 output, becomes high. At this time, the string select line operation is performed by inputting an address, which is an external input signal, to the SS-predecoder, and the SSO selected by the predecoder is Low (not selected SS1. SSn is all high, and NOde B is discharged through the enhancement transistor PSSTRO (GND), so String Select Line 0 becomes High (all unselected String Select Line is Low) by Inverter SSINVO. Cell string 1 is selected by turning on SSTRO. In the operation of the word line, an address, which is an external input signal, is input to the S-Pre decoder, and one output SO selected by the pre decoder is Low (GND), and Node D is an enhancement transistor in the row decoder 200 of FIG. Discharged (GND) via PSTRO, word line 0 goes low (unselected word lines high) by inverters SINVO and SINV1, and CTRO connected to Cell String 1 is selected. At this time, if CTRO is an enhancement transistor, it is turned off. If CTRO is a deflection type, current is turned on. Thus, a path is formed between the sense transistor connected to the bit line through CTR7 and ground, which are already turned on. Therefore, the sense amplifier reads Data 0 and Data 1 by two MOde when the current path between the sense amplifier and ground is formed or not, and represents the dummy cell shape of the present invention.

In Figure 3, the cell string line and the dummy string line are selected by SSL 0 and SSL 1, and only the bit line cells are selected by the word line at the same array location, the word line is disconnected from the last cell of the bit line and the dummy cell selection sheet is A dummy string current was allowed to flow through the power supply voltage. Conventionally, the channel length of the dummy string transistor is larger than the cell so that the number of transistors of the cell string and the number of transistors of the dummy string are generally the same so that the dummy string current is half of the bit line string current. Due to this change, the ratio between the dummy string current and the bit line string current was weak. However, in the present invention, since the dummy bit line and the bit line are selected at the same array position by the string line, the AC response time due to the loading difference is improved. In addition, the loading effect can be reduced by allowing the dummy cell positioned in the Prei side to be controlled like a normal cell in the cell array block so that a core rule such as a normal cell can be applied in a process.

Claims (3)

It has a plurality of bit lines and a plurality of word lines, unit memory cells are gathered to form a memory string, and a memory string consisting of a plurality of unit memory cells is formed where bit lines and word lines meet, and an external address signal. A method of arranging a memory having a structure in which a memory string is selected by the method, wherein the signal of the string selection line operated by the selected row decoder is arranged in such a manner that the string of the normal array and the dummy string of the reference voltage generation circuit part are simultaneously selected. Characterized in that. The method of claim 1, wherein the string select lines are shared, but the word lines are separated so as to adjust a voltage level of the dummy string. The method of claim 1, wherein the number of dummy strings is less than or equal to the number of sense amplifiers.