KR970014280A - Method of forming multi-layer pattern of optical path control device - Google Patents

Method of forming multi-layer pattern of optical path control device Download PDF

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KR970014280A
KR970014280A KR1019950027519A KR19950027519A KR970014280A KR 970014280 A KR970014280 A KR 970014280A KR 1019950027519 A KR1019950027519 A KR 1019950027519A KR 19950027519 A KR19950027519 A KR 19950027519A KR 970014280 A KR970014280 A KR 970014280A
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South Korea
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layer
optical path
forming
path control
pattern
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KR1019950027519A
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Korean (ko)
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KR0170950B1 (en
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김준모
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배순훈
대우전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

본 발명은 광로 조절 장치의 기판상에 적층된 멤브레인, 하부전극, 변형부 및 상부 전극을 상이한 크기로 패터닝시키기 위한 방법에 관한 것으로서, 상기 기판상에 순차적으로 형성된 제1층 및 제2층상에 감광층을 형성시키고 패터닝시키는 제1단계와, 상기 패터닝된 감광층을 마스크로 하여 상기 제2층을 패터닝시키는 제2단계와, 상기 감광층을 유기 실란 부가 공정에 의하여 실란화층으로 전환시키는 제3단계와, 그리고 상기 유기 실란 부가 공정에 의하여 형성된 상기 실란화층을 마스크로 하여 상기 제1층을 패터닝시킨 후 실란화층을 제거하는 제4단계로 이루어지며 이에 의해서 간단한 공정에 의하여 상이한 크기의 패턴을 형성시킬 수 잇다.The present invention relates to a method for patterning a membrane, a lower electrode, a deformable portion, and an upper electrode laminated on a substrate of an optical path control apparatus to different sizes, and is provided on a first layer and a second layer sequentially formed on the substrate. A first step of forming and patterning a layer, a second step of patterning the second layer using the patterned photosensitive layer as a mask, and a third step of converting the photosensitive layer into a silanized layer by an organic silane addition process And a fourth step of removing the silanization layer after patterning the first layer using the silanization layer formed by the organosilane addition process as a mask, thereby forming patterns of different sizes by a simple process. Can be.

Description

광로 조절 장치의 다층 패턴 형성 방법Method of forming multi-layer pattern of optical path control device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도 (가) 내지 (라)는 본 발명에 따른 다층 패턴 형성 방법을 순차적으로 도시한 공정도.3 (a) to (d) is a process chart sequentially showing a method for forming a multi-layer pattern according to the present invention.

제4도는 본 발명을 수행하기 위한 유기 실란 부가 공정을 나타낸 흐름도.4 is a flow chart showing an organosilane addition process for carrying out the present invention.

Claims (8)

기판(21) 상에 적층된 제1층(22) 및 제2층(23)을 상이한 크기의 패턴으로 형성시키기 위한 광로 조절 장치의 다층 패턴 형성 방법에 있어서, 상기 기판(21)상에 순차적으로 적측된 제1층(22) 및 제2층(23)상에 감광층(24)을 형성시키고 패터닝시키는 제1단계와, 상기 패터닝된 감광층(24)을 마스크로 하여 상기 제2층(23)을 패터닝시키는 제2단계와, 상기 감광층(24)을 유기 실란 부가 공정에 의하여 실란화층(24´)으로 전환시키는 제3단계와, 그리고 상기 실란화층(24´)을 마스크로 하여 상기 제1층(22)을 패터닝시킨후 상기 실란화층(24´)을 제거하는 제4단계로 이루어진 것을 특징으로 하는 광로 조절 장치의 다층 패턴 형성 방법.In the method of forming a multi-layer pattern of the optical path control apparatus for forming the first layer 22 and the second layer 23 stacked on the substrate 21 in a pattern having a different size, sequentially on the substrate 21 A first step of forming and patterning the photosensitive layer 24 on the stacked first layer 22 and the second layer 23, and using the patterned photosensitive layer 24 as a mask, the second layer 23 ) Is patterned, the third step of converting the photosensitive layer 24 to the silanized layer 24 'by an organic silane addition process, and the silanized layer 24' as a mask. And a fourth step of removing the silanized layer (24 ') after patterning the first layer (22). 제1항에 있어서, 상기 유기실란 부가 공정은 상기 제2층(23)상에 잔존하는 감광층(24)을 노광시킨 후, 상기 노광된 감광층(24)을 액체 상태 또는 기체 상태의 실리레이션 에이전트에 침지시키거나 노출시킴으로서 수행되는 것을 특징으로 하는 광로 조절 장치의 다층 패턴 형성 방법.The method of claim 1, wherein the organosilane addition process exposes the photosensitive layer 24 remaining on the second layer 23, and then the exposed photosensitive layer 24 is in a liquid or gaseous state. A method of forming a multi-layer pattern of an optical path control apparatus, characterized in that it is carried out by immersing or exposing to an agent. 제2항에 있어서, 상기 실리레이션 에이전트는 유기 실란기를 함유하는 화합물로 이루어져 있는 것을 특징으로 하는 광로 조절 장치의 다층 패턴 형성 방법.The method of claim 2, wherein the silicing agent comprises a compound containing an organic silane group. 제3항에 있어서, 상기 실리레이션 에이전트는 헥사메틸디실라잔(HMDS), n,n-디메틸라미노 트리메틸실라잔(TMSDMA), 디클로로메틸실란(DCMS;), 또는 비스-디메틸라미노-메틸실란(D-DMAMS)중 적어도 하나의 화합물로 이루어져 있는 것을 특징으로 하는 광로 조절 장치의 다층 패턴 형성 방법.The method of claim 3, wherein the silicide agent is hexamethyldisilazane (HMDS), n, n-dimethyllamino trimethylsilazane (TMSDMA), dichloromethylsilane (DCMS;), or bis-dimethylramino-methyl A method of forming a multilayer pattern of an optical path control device, characterized in that it consists of at least one compound of silane (D-DMAMS). 제1항 내지 제4항 중 적어도 하나의 항에 있어서, 상기 감광층(24)은 상기 실리레이션 에이전트의 유기 실란기와 반응하여 팽윤 현상을 나타내는 포토 레지스트로 이루어져 있는 것을 특징으로 하는 광로 조절장치의 다층 패턴 형성방법.5. The multilayer of an optical path control apparatus according to any one of claims 1 to 4, wherein the photosensitive layer (24) is made of a photoresist that reacts with an organic silane group of the siliciding agent and exhibits swelling. Pattern formation method. 제5항에 있어서, 상기 포토 레지스트는 디아조화합물을 함유하는 노볼락계 포토레지스트로 이루어져 있는 것을 특징으로 하는 광로 조절장치의 다층패턴 형성 방법.6. The method of claim 5, wherein the photoresist is made of a novolak-based photoresist containing a diazo compound. 제1항에 있어서, 상기 제1층(23) 및 제2층(24)은 실리콘 산화물(SiO)과, 실리콘 질화물(SiN2또는 Si3N4)과 인이 도핑된 실리콘 산화물(PSG) 또는 이들 중 하나로 구성된 절연 물질로 이루어진 것을 특징으로 하는 광로 조절장치의 다층 패턴 형성 방법.The method of claim 1, wherein the first layer 23 and the second layer 24 include silicon oxide (SiO), silicon nitride (SiN 2 or Si 3 N 4 ), and phosphorus doped silicon oxide (PSG) or Method for forming a multi-layer pattern of the optical path control device, characterized in that made of an insulating material composed of one of these. 제7항에 있어서, 상기 제1층(23)은 플라즈마 이온 식각 공정에 의하여 패터닝되는 것을 특징으로 하는 광로 조절장치의 다층 패턴 형성 방법.The method of claim 7, wherein the first layer (23) is patterned by a plasma ion etching process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950027519A 1995-08-30 1995-08-30 Method for patterning multilayer of optical projection system KR0170950B1 (en)

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KR1019950027519A KR0170950B1 (en) 1995-08-30 1995-08-30 Method for patterning multilayer of optical projection system

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