KR100266084B1 - Method for forming conductive line - Google Patents

Method for forming conductive line Download PDF

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KR100266084B1
KR100266084B1 KR1019970058974A KR19970058974A KR100266084B1 KR 100266084 B1 KR100266084 B1 KR 100266084B1 KR 1019970058974 A KR1019970058974 A KR 1019970058974A KR 19970058974 A KR19970058974 A KR 19970058974A KR 100266084 B1 KR100266084 B1 KR 100266084B1
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wiring
reflective layer
layer
photoresist pattern
colorant
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KR1019970058974A
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Korean (ko)
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KR19990039032A (en
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강상우
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for an interconnection is to prevent halation phenomenon from being produced in a photoresist film, thereby reducing a width of the interconnection. CONSTITUTION: After an interconnection layer(23) is formed on a substrate(21) through a sputtering or chemical vapor deposition, an oxide silicon is deposited on the interconnection layer to form a half-reflective layer(25), the oxide silicon containing a coloring agent having a property capable of absorbing an incident ray of a constant wavelength and an energy band gap of a constant range. A photoresist pattern(27) is formed on the half-reflective layer to expose a desired portion of the half-reflective layer. The half-reflective layer and an exposed portion of the interconnection layer are patterned using the photoresist pattern as a mask to form an interconnection, and the photoresist pattern is removed. The light reflected when the exposing procedure is absorbed by the half-reflective layer.

Description

반도체장치의 배선 형성 방법Wiring Formation Method of Semiconductor Device

본 발명은 반도체장치의 배선 형성 방법에 관한 것으로서, 특히,The present invention relates to a wiring forming method of a semiconductor device, and in particular,

노광시 입사광의 반사를 감소하여 미세한 배선을 형성할 수 있는 반도체장치의 배선 형성 방법에 관한 것이다.The present invention relates to a wiring forming method of a semiconductor device capable of forming fine wiring by reducing reflection of incident light during exposure.

반도체소자의 집적도가 증가함에 따라 단위 셀의 크기가 작아진다. 단위 셀의 크기의 축소에 따라 셀영역 내의 배선의 선폭도 감소하게 된다. 배선의 폭이 감소하면 공정이 어려울 뿐만 아니라 저항이 증가되는 문제점이 있다.As the degree of integration of semiconductor devices increases, the unit cell size decreases. As the size of the unit cell is reduced, the line width of the wiring in the cell region is also reduced. If the width of the wiring is reduced, not only is the process difficult, but there is a problem that the resistance is increased.

그러므로, 저항을 증가시키지 않으면서 배선의 폭을 감소시켜 단위 셀의 크기를 감소시키므로 집적도를 향상시키는 기술이 개발되고 있다.Therefore, a technique for improving the degree of integration has been developed because the width of the wiring is reduced to reduce the unit cell size without increasing the resistance.

도 1a 내지 도 1c는 종래 기술에 따른 반도체장치의 배선 형성방법을 도시하는 공정도이다.1A to 1C are process drawings showing a wiring forming method of a semiconductor device according to the prior art.

도 1a를 참조하면, 기판(11) 상에 알루미늄 등의 도전 물질을 스퍼터링 방법 또는 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 증착하여 배선층(13)을 형성한다. 상기에서 기판(11)은 불순물 확산영역 또는 하부 배선을 덮는 층간절연막이다.Referring to FIG. 1A, a wiring layer 13 is formed on a substrate 11 by depositing a conductive material such as aluminum by a sputtering method or a chemical vapor deposition (hereinafter, referred to as CVD) method. The substrate 11 is an interlayer insulating film covering the impurity diffusion region or the lower wiring.

도 1b를 참조하면, 배선층(13) 상에 포토레지스트를 도포한다. 그리고, 포토레지스트를 노광하고 현상하여 배선층(13)의 소정 부분을 노출시키는 포토레지스트 패턴(15)을 형성한다.Referring to FIG. 1B, a photoresist is applied on the wiring layer 13. Then, the photoresist is exposed and developed to form a photoresist pattern 15 exposing a predetermined portion of the wiring layer 13.

도 1c를 참조하면, 포토레지스트 패턴(15)을 마스크로 사용하여 배선층(13)의 노출된 부분을 반응성 이온 식각 등의 이방성 식각 방법으로 기판(11)이 노출되도록 제거하여 배선(14)을 형성한다.Referring to FIG. 1C, using the photoresist pattern 15 as a mask, an exposed portion of the wiring layer 13 is removed to expose the substrate 11 by an anisotropic etching method such as reactive ion etching to form the wiring 14. do.

그리고, 배선(14) 상에 잔류하는 포토레지스트 패턴(15)을 제거한다.Then, the photoresist pattern 15 remaining on the wiring 14 is removed.

그러나, 상술한 종래의 배선형성방법은 감광막 노광시 입사광이 배선층에 의해 반사되어 감광막에 헐레이션(halation) 현상이 발생되므로 배선의 선폭이 증가되는 문제점이 있었다.However, the above-described conventional wiring forming method has a problem in that the line width of the wiring is increased because incident light is reflected by the wiring layer during photosensitive film exposure and a halation phenomenon occurs in the photosensitive film.

따라서, 본 발명의 목적은 입사광에 의해 감광막에 헐레이션 현상이 발생되는 것을 방지하여 배선의 선폭을 감소시킬 수 있는 반도체장치의 배선 형성 방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a method for forming a wiring in a semiconductor device which can reduce the line width of the wiring by preventing the halation phenomenon from occurring on the photosensitive film due to incident light.

상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 배선 형성 방법은 기판 상에 배선층을 형성하는 공정과, 상기 배선층 상에 착색제가 포함된 산화실리콘을 증착하여 반반사층을 형성하는 공정과, 상기 반반사층 상에 포토레지스트를 도포하고 노광 및 현상하여 소정 부분을 노출시키는 포토레지스트 패턴을 형성하는 공정과, 상기 포토레지스트 패턴을 마스크로 사용하여 상기 반반사층 및 배선층을 패터닝하여 배선을 형성하는 공정과, 상기 배선 상의 포토레지스트 패턴을 제거하는 공정을 구비한다.The wiring forming method of the semiconductor device according to the present invention for achieving the above object is a step of forming a wiring layer on a substrate, a step of forming a semi-reflective layer by depositing silicon oxide containing a colorant on the wiring layer, and the anti Forming a photoresist pattern by applying a photoresist on a reflective layer, exposing and developing the photoresist to expose a predetermined portion; patterning the semi-reflective layer and the wiring layer using the photoresist pattern as a mask to form wiring; The process of removing the photoresist pattern on the said wiring is provided.

도 1a 내지 도 1c는 종래 기술에 따른 반도체장치의 배선 형성방법을 도시1A to 1C illustrate a wiring forming method of a semiconductor device according to the prior art.

하는 공정도Process chart

도 2a 내지 도 2c는 본 발명에 따른 반도체장치의 배선 형성 방법을 도시하는 공정도2A to 2C are process drawings showing a wiring forming method of a semiconductor device according to the present invention.

이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명에 따른 반도체장치의 배선 형성 방법을 도시하는 공정도이다.2A to 2C are process diagrams showing the wiring formation method of the semiconductor device according to the present invention.

도 2a를 참조하면, 기판(21) 상에 알루미늄 등의 도전 물질을 스퍼터링 방법 또는 CVD 방법으로 증착하여 배선층(23)을 형성한다. 상기에서 기판(11)은 불순물 확산영역 또는 하부 배선을 덮는 층간절연막이다.Referring to FIG. 2A, a wiring layer 23 is formed by depositing a conductive material such as aluminum on the substrate 21 by a sputtering method or a CVD method. The substrate 11 is an interlayer insulating film covering the impurity diffusion region or the lower wiring.

그리고, 배선층(23) 상에 반반사층(25)을 형성한다. 반반사층(25)을 산화실리콘에 소정 량의 착색제(coloring agent)를 첨가하여 비정질 구조로 형성한다.Then, the antireflection layer 25 is formed on the wiring layer 23. The semi-reflective layer 25 is formed into an amorphous structure by adding a predetermined amount of coloring agent to the silicon oxide.

상기에서 착색제는 이 후에 진행될 노광 공정에서 사용되는 광이 G-선(파장이 436nm)인 경우 2.4∼3.2eV의 에너지 밴드 갭을 갖는 물질을 사용하고, I-선(파장이 365nm)인 경우 3.0∼3.8eV의 에너지 밴드 갭을 갖는 물질, 즉, GaN을 등을 사용하며, KrF선(파장이 248nm)인 경우 4.5∼5.5eV의 에너지 밴드 갭을 갖는 물질을 사용하고, ArF선(파장이 193nm)인 경우 6.0∼6.8eV의 에너지 밴드 갭을 갖는 물질, 즉, AlN 등을 사용한다.In the above, the colorant uses a material having an energy band gap of 2.4 to 3.2 eV when the light used in the subsequent exposure process is G-ray (wavelength is 436 nm), and 3.0 when I-ray (wavelength is 365 nm). A material having an energy band gap of ˜3.8 eV, that is, GaN is used, and in the case of a KrF line (wavelength is 248 nm), a material having an energy band gap of 4.5 to 5.5 eV is used, and an ArF line (wavelength is 193 nm). ), A material having an energy band gap of 6.0 to 6.8 eV, that is, AlN or the like is used.

도 2b를 참조하면, 반반사층(25) 상에 포토레지스트를 도포한다. 그리고, 포토레지스트를 노광하고 현상하여 반반사층(25)의 소정 부분을 노출시키는 포토레지스트 패턴(27)을 형성한다. 상기에서 노광시 입사되는 광은 포토레지스트를 노광한 후 반반사층(25)에 흡수되어 반사에 의한 헐레이션을 방지한다. 그러므로, 포토레지스트 패턴(27)에 의해 반반사층(25)이 미세한 선폭을 갖고 노출된다.Referring to FIG. 2B, a photoresist is applied on the semireflective layer 25. Then, the photoresist is exposed and developed to form a photoresist pattern 27 exposing a predetermined portion of the semi-reflective layer 25. The light incident upon exposure is absorbed by the semi-reflective layer 25 after the photoresist is exposed to prevent halation due to reflection. Therefore, the semireflective layer 25 is exposed with a fine line width by the photoresist pattern 27.

즉, 반반사층(25)이 2.4∼3.2eV의 에너지 밴드 갭을 갖는 물질을 포함하면 G-선(파장이 436nm)의 입사광을 흡수하고, 3.0∼3.8eV의 에너지 밴드 갭을 갖는 물질, 즉, GaN을 등을 포함하면 I-선(파장이 365nm)의 입사광을 흡수한다. 또한, 반반사층(25)이 4.5∼5.5eV의 에너지 밴드 갭을 갖는 물질을 포함하면 KrF선(파장이 248nm)의 입사광을 흡수하고, 6.0∼6.8eV의 에너지 밴드 갭을 갖는 물질, 즉, AlN 등을 포함하면 ArF선(파장이 193nm)의 입사광을 흡수한다.That is, when the anti-reflective layer 25 includes a material having an energy band gap of 2.4 to 3.2 eV, it absorbs incident light of G-line (wavelength of 436 nm), and a material having an energy band gap of 3.0 to 3.8 eV, that is, Including GaN absorbs incident light of I-line (wavelength: 365 nm). In addition, when the antireflective layer 25 includes a material having an energy band gap of 4.5 to 5.5 eV, it absorbs incident light of KrF line (wavelength of 248 nm), and has a material having an energy band gap of 6.0 to 6.8 eV, that is, AlN. And the like absorb the incident light of the ArF line (wavelength: 193 nm).

도 2c를 참조하면, 포토레지스트 패턴(27)을 마스크로 사용하여 반반사층(25) 및 배선층(23)의 노출된 부분을 반응성 이온 식각 등의 이방성 식각 방법으로 기판(21)이 노출되도록 제거하여 배선(26)을 형성한다.Referring to FIG. 2C, by using the photoresist pattern 27 as a mask, the exposed portions of the semi-reflective layer 25 and the wiring layer 23 are removed to expose the substrate 21 by an anisotropic etching method such as reactive ion etching. The wiring 26 is formed.

그리고, 배선(26) 상에 잔류하는 포토레지스트 패턴(27)을 제거한다.Then, the photoresist pattern 27 remaining on the wiring 26 is removed.

상술한 바와 같이 본 발명에 따른 반도체장치의 배선 형성 방법은 배선층 상에 반반사층을 형성하고, 이 반반사층 상에 포토레지스트를 도포하므로 노광할 때 입사광이 반반사층에 반사되지 않고 흡수되어 미세한 포토레지스트 패턴을 형성한다.As described above, in the wiring forming method of the semiconductor device according to the present invention, a semi-reflective layer is formed on the wiring layer and a photoresist is applied on the semi-reflective layer. Form a pattern.

따라서, 본 발명은 미세한 포토레지스트 패턴을 사용하여 배선층을 패터닝하므로 배선의 선폭을 감소시킬 수 있는 잇점이 있다.Therefore, the present invention has the advantage of reducing the line width of the wiring because the wiring layer is patterned using a fine photoresist pattern.

Claims (7)

기판 상에 배선층을 형성하는 공정과.Forming a wiring layer on the substrate; 상기 배선층 상에 일정범위의 에너지 밴드갭을 가지고 노광 시에 일정 파장의 입사광만을 흡수하는 성질을 갖는 착색제가 포함된 산화실리콘을 증착하여 반반사층을 형성하는 공정과,Forming a semi-reflective layer by depositing silicon oxide containing a colorant having a range of energy bandgap on the wiring layer and having a property of absorbing only incident light having a predetermined wavelength upon exposure; 상기 반반사층 상에 소정 부분을 노출시키는 포토레지스트 패턴을 형성하는 공정과,Forming a photoresist pattern exposing a predetermined portion on the semi-reflective layer; 상기 포토레지스트 패턴을 마스크로 사용하여 상기 반반사층 및 배선층르 패터닝하여 배선을 형성하는 공정과,Forming a wiring by patterning the semi-reflective layer and the wiring layer using the photoresist pattern as a mask; 상기 포토레지스트 패턴을 제거하는 공정을 구비하는 반도체장치의 배선 형성 방법.And a step of removing the photoresist pattern. 청구항 1에 있어서The method according to claim 1 상기 착색제는 2.4∼3.2eV의 에너지 밴드 갭을 갖는 물질로 상기 노광시 G- 선(파장이 436nm)의 광을 사용하는 반도체장치의 배선 형성 방법.And wherein the colorant is a material having an energy band gap of 2.4 to 3.2 eV, and uses light having a G-line (wavelength of 436 nm) during the exposure. 청구항 1에 있어서The method according to claim 1 상기 착색제는 3.0∼3.8eV의 에너지 밴드 갭을 갖는 물질로 상기 노광시 I-선(파장이 365nm)의 광을 사용하는 반도체장치의 배선 형성 방법.And wherein the colorant is a material having an energy band gap of 3.0 to 3.8 eV, and uses light of an I-line (365 nm wavelength) during the exposure. 청구항 3에 있어서The method according to claim 3 상기 착색제로 GaN을 사용하는 반도체장치의 배선 형성방법.A wiring forming method for a semiconductor device using GaN as the colorant. 청구항 1에 있어서The method according to claim 1 상기 착색제는 4.5∼5.5eV의 에너지 밴드 갭을 갖는 물질로 상기 노광시 KrF선(파장이 248nm)의 광을 사용하는 반도체 장치의 배선 형성 방법.And wherein the colorant is a material having an energy band gap of 4.5 to 5.5 eV, and uses KrF rays (wavelength of 248 nm) during exposure. 청구항 1에 있어서The method according to claim 1 상기 착색제는 6.0∼6.8eV의 에너지 밴드 갭을 갖는 물질로 상기 노광시 ArF선(파장이 193nm)의 광을 사용하는 반도체장치의 배선 형성 방법.And wherein the colorant is a material having an energy band gap of 6.0 to 6.8 eV and uses light of an ArF line (wavelength of 193 nm) during the exposure. 청구항 6에 있어서The method according to claim 6 상기 착색제로 AIN을 사용하는 반도체장치의 배선 형성 방법.A wiring forming method for a semiconductor device using AIN as the colorant.
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098078A (en) * 1995-06-16 1997-01-10 Matsushita Electron Corp Forming method of pad for lead-out

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098078A (en) * 1995-06-16 1997-01-10 Matsushita Electron Corp Forming method of pad for lead-out

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