KR970013909A - Reception device for souce synehronous transmition data - Google Patents

Reception device for souce synehronous transmition data Download PDF

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Publication number
KR970013909A
KR970013909A KR1019950024219A KR19950024219A KR970013909A KR 970013909 A KR970013909 A KR 970013909A KR 1019950024219 A KR1019950024219 A KR 1019950024219A KR 19950024219 A KR19950024219 A KR 19950024219A KR 970013909 A KR970013909 A KR 970013909A
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KR
South Korea
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signal
read
output
write
data
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KR1019950024219A
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Korean (ko)
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KR0152397B1 (en
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박경
한종석
심원세
한우종
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양승택
한국전자통신연구소
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Publication of KR970013909A publication Critical patent/KR970013909A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

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  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

본 발명은 독립 동기 방식에 의해서 동기되는 시스템에서 수신되는 데이타를 수신단의 지역 클록으로 파이프라인 처리가 이루어질 수 있도록 한 근원지 동기 전송 방식 데이타 수신장치에 관한 것이다.The present invention relates to a source-synchronous transmission data receiving apparatus that allows pipeline processing to be performed by a system synchronized with an independent synchronization method to a local clock of a receiving end.

이러한 본 발명은 송신단에서 출력되는 데이타와 패킷 동기신호를 수신되는 플릿 동기신호에 래치시키는 래치부와, 래치부에서 출력되는 채킷 동기신호와 수신되는 플릿 동기신호에 따라 쓰기 제어신호를 발생하는 쓰기 제어기와, 래치부에서 출력되는 패킷 동기신호와 수신단 클럭을 동기화 시키는 동기화기와, 동기화기에서 출력되는 신호와 듀얼 포트 기억소자의 상태신호에 따라 수신단의 동작 클록을 기준으로 하는 읽기 시작점 선택신호를 출력하여 파이프라인 처리가 가능토록 하는 읽기 시점 선택부와, 읽기 시점 선택부에서 출력되는 신호에 따라 읽기 제어신호를 발생하는 읽기 제어기와, 쓰기 제어기의 출력신호에 의해 상기 래치부에서 출력되는 데이타를 기록하고 읽기 제어기에서 출력되는 신호에 의해 기록된 데이타를 판독하여 출력하는 듀얼 포트 기억소자로 이루어진다.The present invention is a latch controller for latching data and packet synchronization signals outputted from a transmitting end to a received flit synchronization signal, and a write controller for generating a write control signal according to the received channel synchronization signal and the received flit synchronization signal. And a synchronizer for synchronizing the packet synchronizing signal outputted from the latch unit with the receiving end clock, and outputting a read start point selection signal based on the operation clock of the receiving end according to the signal outputted from the synchronizer and the status signal of the dual port memory device. A read point selector for allowing pipeline processing, a read controller for generating a read control signal in accordance with a signal output from the read point selector, and data output from the latch unit by an output signal of the write controller, Read and output the data recorded by the signal output from the read controller It comprises a dual-port storage element.

Description

근원지 동기전송 방식 데이타 수신장치(Reception Device for Souce synehronous transmition data)Reception device for souce synehronous transmition data

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 3 도는 본 발명에 의한 근원지 동기 전송 방식 데이타 수신장치 블록 구성도.3 is a block diagram of a source-synchronous data transmission device according to the present invention.

Claims (2)

송신단에서 출력되는 데이타와 패킷 동기신호를 수신되는 플릿 동기신호에 래치시키는 래치부와, 상기 래치부에서 출력되는 채킷 동기신호와 수신되는 플릿 동기신호에 따라 쓰기 어드레스와 쓰기 신호 및 테일 신호를 발생하여 쓰기 동작을 제어하는 쓰기 제어기와, 상기 래치부에서 출력되는 패킷 동기신호와 수신단의 클럭을 동기시키는 동기화기와, 상기 동기화기에서 출력되는 신호와 듀얼 포트 기억소자의 상태신호에 따라 수신단의 동작 클록을 기준으로 하는 읽기 시작점 선택 신호를 출력하여 파이프라인 처리가 가능토록 하는 읽기 시점 선택부와, 상기 읽기 시점 선택부에서 출력되는 신호에 따라 읽기 제어신호를 발생하는 읽기 제어기와, 상기 쓰기 제어기의 출력신호에 의해 상기 래치부에서 출력되는 데이타를 기록하고 상기 읽기 제어기에서 출력되는 신호에 의해 기록된 데이타를 판독하여 출력하는 듀얼 포트 기억소자를 포함하여 구성된 것을 특징으로 하는 근원지 동기 전송 방식 데이타 수신장치.A latch unit for latching the data and packet synchronization signals outputted from the transmitter to the received flit synchronization signal, and generating a write address, a write signal, and a tail signal according to the chunk synchronization signal outputted from the latch unit and the received flit synchronization signal; A write controller for controlling a write operation, a synchronizer for synchronizing the packet synchronizing signal output from the latch unit with a clock of the receiving end, and an operating clock of the receiving end according to the signal output from the synchronizer and the status signal of the dual port memory device. A read point selector for outputting a read start point selection signal as a reference to enable pipeline processing, a read controller for generating a read control signal according to a signal output from the read point selector, and an output signal of the write controller Write data output from the latch unit and control the read A source synchronous transmission scheme data receiving device, characterized in that configured to include a dual-port memory device for reading and outputting the data recorded by the signal output from. 제1항에 있어서, 상기 읽기 시점 선택부는 상기 동기화기에서 출력되는 신호를 수신단 클록에 동기시켜 출력하는 직렬로 연결되는 다수개의 플립플롭과, 상기 다수개의 플립플롭에서 각각 출력되는 신호를 상기 듀얼포트 상태신호에 따라 다중화하여 읽기 시작점 신호로 출력하는 다중화기로 구성된 것을 특징으로 하는 근원지 동기 정송 방식 데이타 수신장치.The dual port of claim 1, wherein the read point selector comprises a plurality of flip-flops connected in series for synchronizing and outputting a signal output from the synchronizer to a receiver clock, and the signals output from the plurality of flip-flops, respectively. A source synchronous transmission method data receiving apparatus, comprising: a multiplexer for multiplexing according to a status signal and outputting the signal as a read start point signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950024219A 1995-08-05 1995-08-05 Reception device for source synchronous transmission data KR0152397B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950024219A KR0152397B1 (en) 1995-08-05 1995-08-05 Reception device for source synchronous transmission data

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Application Number Priority Date Filing Date Title
KR1019950024219A KR0152397B1 (en) 1995-08-05 1995-08-05 Reception device for source synchronous transmission data

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KR970013909A true KR970013909A (en) 1997-03-29
KR0152397B1 KR0152397B1 (en) 1998-11-02

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