KR970013758A - Negative logic circuit and negative logic sum to minimize chip layout area - Google Patents

Abstract

The present invention relates to a negative logic circuit and a negative logic circuit using a CMOS circuit. Negative logical circuits having a plurality of logic steps 70, 80, 90, and 100 for receiving at least one common enable signal EN and a plurality of input signals a1 to an, b1 to bn ... A first signal receiving the enable signals and outputting a low logic value when all of the enable signals are high logic values and outputting a common signal having a high logic value when at least one of the enable signals is a low logic value Logic step 70, all other logic steps respectively receive the common signal and a plurality of input signals to output the common signal when all of the input signals are high logic value and input at least one or more of the input signals Outputs a high logic value when the signal is a low logic value. A negative logic circuit having a plurality of logic steps 170, 180, 190, and 200 for receiving at least one common enable signal EN and a plurality of input signals a1 to an, b1 to bn ... A first logic for receiving the enable signals and outputting a common signal having a high logic value when all of the enable signals are low logic values and outputting a common signal having a low logic value when at least one of the enable signals is a high logic value And all other logic steps respectively receive the common signal and a plurality of input signals to output the common signal when all of the input signals have a low logic value and at least one of the input signals is high. Outputs low logic value when it is a logic value.

Description

Negative Logic Circuit and Negative Logic Circuit to Minimize Chip Rayout Area

Since this is an open matter, no full text was included.

Claims (20)

A negative logic circuit for receiving first and second input signals and performing a negative logic multiplication, comprising: inverter means for receiving the first input signal and inverting it to output a first signal; And passage means for outputting a high logic value when the second input signal has a low logic value and outputting the first signal when the second input signal has a high logic value. 2. The method of claim 1, wherein the passage means comprises first and second MOS transistors, the source of the first MOS transistor is connected to a supply voltage, and the source of the second MOS transistor is the first signal. And the gates of the first and second MOS transistors are connected to the second input signal, and the drains of the first and second MOS transistors are connected in common. The negative logic circuit of claim 2, wherein the first MOS transistor is a PMOS transistor, and the second MOS transistor is an NMOS transistor. A negative logic circuit for receiving a plurality of input signals and performing a negative logic multiplication thereof, comprising: an inverter means for receiving one of the plurality of input signals, inverting the same, and outputting a first signal; And a plurality of passage means for outputting a high logic value when the input signal has a low logic value, and for passing the output signal of the preceding stage when the input signal has a low logic value. And the first signal is passed when the input signal inputted to the device has a high logic value. 5. The method of claim 4, wherein the passage means comprises first and second MOS transistors, the source of the first MOS transistor is connected to a supply voltage, and the gates of the first and second MOS transistors are formed. And an input of one of the input signals, wherein the drains of the first and second MOS transistors are connected in common and connected to the source of the ANMOS transistor of the passage means in a next step. The negative logic circuit of claim 5, wherein the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor. 7. In a negative logic circuit having at least one common enable signal and a plurality of logic steps for receiving a plurality of input signals, a first logic step of the plurality of logic steps receives the common enable signals. And an inverter means for receiving one of the enable signals and inverting it to output the first signal, and outputting a high logic value when the enable signal has a low logic value and a high logic value. There are a plurality of passage means for passing the output signal of the preceding stage, wherein the passage means of the first stage of the passage means passes the first signal when the enable signal input in the first stage has a high logic value. All other logic steps receive the output of the first logic step and the input signals, respectively, and the input signal has a low logic value. There are a plurality of passage means for outputting a high logic value when passing and passing the output signal of the preceding stage when the high logic value is obtained. The passage means of the first stage among the plurality of passage means means that the input signal input at the first stage is high. A negative logic circuit characterized in that it passes the output of the first step when having a logic value. The method of claim 7, wherein the passage means comprises first and second MOS transistors, a source of the first MOS transistor is connected to a supply voltage, and gates of the first and second MOS transistors are connected to each other. Connected to one of the common enable signals or one of the plurality of input signals, and the drains of the first and second MOS transistors are commonly connected to the NMOS of the passage means of the next stage. Negative logic circuit, characterized in that connected to the source of the transistor. The negative logic circuit of claim 8, wherein the first MOS transistor is a PMOS transistor, and the second MOS transistor is an NMOS transistor. In a negative logic circuit having at least one common enable signal and a plurality of logic steps, a first logic step of the plurality of logic steps receives the common enable signals to receive the enable signals. All of them have a low logic value when the high logic value and at least one of the enable signals of the enable signal outputs a common signal having a high logic value when the low logic value, and all other logic steps are the same Receives a plurality of input signals and outputs the common signal when all of the input signals are high logic values, and outputs a high logic value when at least one of the input signals is a low logic value. Negative logical circuit characterized in that. A negative logic circuit for receiving first and second input signals and negating and logically combining the first and second input signals, the negative logic circuit comprising: inverter means for receiving the first input signal and inverting the first input signal to output the first signal; And passage means for outputting a low logic value when the second input signal has a high logic value and outputting the first signal when the second input signal has a low logic value. 12. The method of claim 11, wherein the passage means comprises first and second MOS transistors, wherein the source of the second MOS transistor is connected to a ground voltage, and the source of the first MOS transistor is the first signal. And the gates of the first and second MOS transistors are connected to the second input signal, and the drains of the first and second MOS transistors are connected in common. The negative logic circuit of claim 12, wherein the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor. A negative logic circuit for receiving a plurality of input signals and performing a negative logic sum, the negative logic circuit comprising: inverter means for receiving one of a plurality of input signals, inverting the same, and outputting a first signal; And a plurality of passage means for outputting a low logic value when the input signal has a high logic value, and for passing the output signal of the preceding stage when the input signal has a high logic value. And passing the first signal when the input signal inputted to the controller has a low logic value. 15. The method of claim 14, wherein the passage means comprises a first, a second MOS transistor, the source of the second MOS transistor is connected to the ground voltage, the gates of the first, the second MOS transistor is The negative logic circuit of claim 1, wherein the first and second MOS transistors are connected in common and connected to a source of a PMOS transistor of a passage means in a next step. 16. The negative logic circuit of claim 15, wherein the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor. In a negative logic circuit having a plurality of logic steps for receiving at least one common enable signal and a plurality of input signals, a first logic step of the plurality of logic steps receives the common enable signals. Inverter means for receiving one of the enable signals and inverting the enable signal and outputting a first signal, and outputting a low logic value when the enable signal has a high logic value and a low logic value when the enable signal has a high logic value. There are a plurality of passage means for passing the output signal of the passage means, the passage means of the first stage of the passage means passes the first signal when the enable signal input in the first stage has a low logic value, All other logic steps receive the output of the first logic step and the input signals and when the input signal has a high logic value There are a plurality of passage means for outputting the low logic value and passing the output signal of the previous stage when the low logic value is obtained. Among the passage means of the first stage, the input signal input in the first stage is low logic. Negative logic circuit, characterized in that passing the output of the first step when having a value. 18. The method of claim 17, wherein the passage means comprises first and second MOS transistors, the source of the second MOS transistor is connected to a ground voltage, and the gates of the first and second MOS transistors are One of the common enable signals or one of the plurality of input signals is connected, and the drains of the first and second MOS transistors are commonly connected to prevent the passage means of the next step. Negative logic circuit, characterized in that connected to the source of the MOS transistor. 19. The negative logic circuit of claim 18, wherein the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor. In a negative logic circuit having at least one common enable signal and a plurality of logic steps, a first logic step of the plurality of logic steps receives the common enable signals to receive all of the enable signals. Is a high logic value when is a low logic value, and outputs a common signal having a low logic value when at least one of the enable signals is at a high logic value, and all other logic steps are the same. Receiving a signal and a plurality of input signals and outputting the common signal when all of the above input signals are low logic values and outputting a low logic value when at least one of the input signals is a high logic value Negative logic circuit, characterized in that. ※ Note: The disclosure is based on the initial application.