KR970013347A - Capacitor self-aligned with investment junction and manufacturing method thereof - Google Patents

Capacitor self-aligned with investment junction and manufacturing method thereof Download PDF

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Publication number
KR970013347A
KR970013347A KR1019950025724A KR19950025724A KR970013347A KR 970013347 A KR970013347 A KR 970013347A KR 1019950025724 A KR1019950025724 A KR 1019950025724A KR 19950025724 A KR19950025724 A KR 19950025724A KR 970013347 A KR970013347 A KR 970013347A
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KR
South Korea
Prior art keywords
layer
oxide film
capacitor
polysilicon layer
manufacturing
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Application number
KR1019950025724A
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Korean (ko)
Inventor
박규찬
이준희
Original Assignee
김광호
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자주식회사 filed Critical 김광호
Priority to KR1019950025724A priority Critical patent/KR970013347A/en
Publication of KR970013347A publication Critical patent/KR970013347A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

매몰접합구가 자기정렬된 캐패시터 및 그의 제조방법에 관한 것으로, 본 발명의 캐패시터는 반도체기판 위에 형성된 산화막, 상기 산화막내에 형성된 접촉구, 상기 접촉구를 채우는 스토리지 노드 및 상기 스토리지노드의 표면에 순차적으로 형성된 유전층 및 플레이트전극을 구비하며, 상기 캐패시터의 접촉구는 스토라지노드를 만들 때 자기정렬되게 한다. 따라서 본 발명에서는 보통과 같이 두 개의 마스크를 쓰지않고 하나의 마스크만으로 만들기 때문에 제작이 용이하고 정렬문제도 발생하지 않는다.The present invention relates to a capacitor in which an investment junction is self-aligned, and to a method of manufacturing the same. The capacitor of the present invention sequentially includes an oxide film formed on a semiconductor substrate, a contact hole formed in the oxide film, a storage node filling the contact hole, and a surface of the storage node. A dielectric layer and a plate electrode formed are provided, and the contact holes of the capacitor are self-aligned when forming the storage node. Therefore, in the present invention, since only one mask is used without two masks as usual, manufacturing is easy and alignment problems do not occur.

Description

매몰접합구가 자기정렬된 캐패시터 및 그의 제조방법Capacitor self-aligned with investment junction and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 캐패시터를 나타내는 단면도이다.2 is a cross-sectional view showing a capacitor according to the present invention.

Claims (6)

캐패시터를 가지는 반도체장치에 있어서, 반도체기판상에 소정부분에 형성된 제1산화막, 상기 제1산화막내에 형성된 접촉구, 상기 접촉구에 인접하는 일측의 산화막에서부터 타측의 산화막에 걸쳐 형성되고 상기 접촉구를 채우며, 상기 접촉구 상에서의 두께가 상기 산화막상에서의 두께보다 얇은 제1도전층, 상기 스토리지전극 표면에 형성된 유전층 및, 상기 유전층의 표면에 형성된 제2 도전층을 구비함을 특징으로 하는 반도체장치의 캐패시터.A semiconductor device having a capacitor, comprising: a first oxide film formed in a predetermined portion on a semiconductor substrate, a contact hole formed in the first oxide film, and an oxide film formed on one side of the oxide film on the other side adjacent to the contact hole; And a first conductive layer having a thickness on the contact hole smaller than that on the oxide film, a dielectric layer formed on the surface of the storage electrode, and a second conductive layer formed on the surface of the dielectric layer. Capacitor. 제1항에 있어서, 상기 제1 도전층은 스토리지노드이고 제2 도전층은 플레이트전극임을 특징으로 하는 반도체장치의 캐패시터.The capacitor of claim 1, wherein the first conductive layer is a storage node and the second conductive layer is a plate electrode. 반도체장치의 캐패시터의 제조방법에 있어서, 반도체기판 상에 제1산화막, 제1폴리실리콘층 및 제2 산화막을 순차적으로 형성하는 단계, 상기 제2산화막을 소정의 마스크를 이용하여 패터닝하는 단계, 결과물 상에 제2 폴리실리콘층을 도포하는 단계, 상기 제2 폴리실리콘층을 이방성식각함과 동시에 상기 제1 폴리실리콘층을 패터닝하여 상기 제1산화막 및 상기 패터닝된 제1 폴리실리콘층의 측벽에 폴리스페이서를 형성하는 단계, 상기 플리스페이서를 마스크로 이용하여, 제1 및 제2산화막을 제거하는 단계, 결과물 상에 제3 폴리실리콘층을 도포하는 단계, 상기 제3 폴리실리콘층 및 상기 제1 폴리실리콘층의 소정부분을 제거하는 형성하는 단계, 및 결과물 상에 유전물질과 제4 폴리실리콘층을 순차적으로 도포하는 단계를 구비함을 특징으로 하는 반도체장치의 캐패시터 제조방법.A method of manufacturing a capacitor of a semiconductor device, the method comprising: sequentially forming a first oxide film, a first polysilicon layer, and a second oxide film on a semiconductor substrate; patterning the second oxide film using a predetermined mask; Applying a second polysilicon layer on the polysilicon layer; anisotropically etching the second polysilicon layer and simultaneously patterning the first polysilicon layer to form a polysilicon layer on sidewalls of the first oxide layer and the patterned first polysilicon layer. Forming a spacer, using the fleece spacer as a mask, removing the first and second oxide films, applying a third polysilicon layer on the resultant, the third polysilicon layer and the first poly Forming and removing a predetermined portion of the silicon layer, and sequentially applying a dielectric material and a fourth polysilicon layer on the resultant. Capacitor manufacturing method of the body device. 제3항에 있어서, 잔존하는 제1 및 제3폴리실리콘층이 스토리지노드이고, 제4 폴리실리콘층은 플레이트전극임을 특징으로 하는 반도체장치의 캐패시터 제조방법.4. The method of claim 3, wherein the remaining first and third polysilicon layers are storage nodes and the fourth polysilicon layer is a plate electrode. 제3항에 있어서, 상기 제1산화막의 식각율은 상기 제2 산화막의 식각률에 비해 작음을 특징으로 하는 반도체장치의 캐패시터의 제조방법.The method of claim 3, wherein the etching rate of the first oxide layer is smaller than that of the second oxide layer. 제3항에 있어서, 상기 접촉구는 자기정렬로 형성됨을 특징으로 하는 반도체장치의 캐패시터의 제조방법.The method of manufacturing a capacitor of a semiconductor device according to claim 3, wherein said contact hole is formed by self-alignment.
KR1019950025724A 1995-08-21 1995-08-21 Capacitor self-aligned with investment junction and manufacturing method thereof KR970013347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950025724A KR970013347A (en) 1995-08-21 1995-08-21 Capacitor self-aligned with investment junction and manufacturing method thereof

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Application Number Priority Date Filing Date Title
KR1019950025724A KR970013347A (en) 1995-08-21 1995-08-21 Capacitor self-aligned with investment junction and manufacturing method thereof

Publications (1)

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KR970013347A true KR970013347A (en) 1997-03-29

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