KR970012748A - Method and apparatus for reducing bitline coupling - Google Patents

Method and apparatus for reducing bitline coupling Download PDF

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Publication number
KR970012748A
KR970012748A KR1019950028401A KR19950028401A KR970012748A KR 970012748 A KR970012748 A KR 970012748A KR 1019950028401 A KR1019950028401 A KR 1019950028401A KR 19950028401 A KR19950028401 A KR 19950028401A KR 970012748 A KR970012748 A KR 970012748A
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KR
South Korea
Prior art keywords
bit lines
memory cells
semiconductor memory
memory device
select signal
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KR1019950028401A
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Korean (ko)
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KR100192569B1 (en
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한상집
곽충근
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김광호
삼성전자 주식회사
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Priority to KR1019950028401A priority Critical patent/KR100192569B1/en
Publication of KR970012748A publication Critical patent/KR970012748A/en
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Publication of KR100192569B1 publication Critical patent/KR100192569B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out

Abstract

1. 청구범위에 기재된 발명이 속하는 기술 분야1. TECHNICAL FIELD OF THE INVENTION

반도체 메모리 장치에 관한 것이다.A semiconductor memory device.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

라이트 모드시 전류증가를 억제하면서 비트라인과 비트라인 사이의 커플링 현상을 감소시킬 수 있는 반도체 메모리 장치 및 방법을 제공한다.Provided are a semiconductor memory device and a method capable of reducing a coupling phenomenon between a bit line and a bit line while suppressing current increase in the write mode.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

반도체 메모리 장치의 라이트 모드시 데이타를 저장 또는 리드할 수 있는 메모리 셀들중 로우선택신호에 의해서 선택된 메모리 셀의 좌우측에 배치된 메모리 셀에 연결된 비트라인들에 전원전압을 인가하기 위한 제1수단과, 컬럼선택신호에 의해 상기 선택된 메모리 셀에 접속된 비트라인에 차이지된 신호들을 방전시키기 위한 제2수단을 포함한다.First means for applying a power supply voltage to bit lines connected to memory cells disposed at left and right sides of a memory cell selected by a row selection signal among memory cells capable of storing or reading data in a write mode of the semiconductor memory device; And second means for discharging signals that are different from the bit line connected to the selected memory cell by a column select signal.

4. 발명의 중요한 용도4. Important uses of the invention

반도체 메모리 장치에 적합하게 사용된다.It is suitably used for semiconductor memory devices.

Description

비트라인 커플링을 감소시키는 방법 및 장치Method and apparatus for reducing bitline coupling

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 비트라인과 그 주변회로도,3 is a bit line and a peripheral circuit diagram according to the present invention,

제5도는 본 발명의 제1실시예에 따라 반도체 메모리 장치를 라이트하기 위한 주변회로도.5 is a peripheral circuit diagram for writing a semiconductor memory device according to the first embodiment of the present invention.

Claims (7)

데이타를 저장 또는 리드할 수 있는 다수의 메모리 셀로 이루어진 메모리 셀 어레이를 가지는 반도체 메모리 장치에 있어서; 상기 메모리 셀들 중 로우선택신호에 의해서 선택된 메모리 셀의 좌우측에 배치된 메모리 셀에 연결된 비트라인들에 전원전압을 인가하기 위한 제1수단과, 상기 비트라인을 제어하기 위한 컬럼선택 신호에 의해 상기 선택된 메모리 셀에 접속된 상기 비트라인에 차아지된 신호들을 방전시키기 위한 제2수단을 가짐을 특징으로 하는 반도체 메모리 장치.A semiconductor memory device having a memory cell array consisting of a plurality of memory cells capable of storing or reading data; First means for applying a power supply voltage to bit lines connected to memory cells disposed on the left and right sides of the memory cells selected by the row select signal among the memory cells, and the selected by the column select signal for controlling the bit lines. And second means for discharging signals charged to the bit line connected to the memory cell. 제1항에 있어서, 상기 제1수단은 상기 비트라인들과 전원전압 사이에 채널들이 직렬로 접속된 제1엔모오스 트랜지스터들을 가지고, 제2수단은 상기 비트라인들 사이에 채널이 직렬로 접속된 제2엔모오스 트랜지스터들을 가짐을 특징으로 하는 반도체 메모리 장치.2. The apparatus of claim 1, wherein the first means has first enMOS transistors in which channels are connected in series between the bit lines and a power supply voltage, and the second means has channels connected in series between the bit lines. And a second NMOS transistor. 제2항에 있어서, 상기 제1엔모오스 트랜지스터들의 게이트 단자에는 인접한 메모리 셀들에 인가되는 컬럼 선택신호가 접속됨을 특징으로 하는 반도체 메모리 장치.The semiconductor memory device of claim 2, wherein a column select signal applied to adjacent memory cells is connected to the gate terminal of the first NMOS transistors. 제2항에 있어서, 상기 메모리 셀들에 인접한 두 비트라인 사이에 접속된 상기 제2엔모오스 트랜지스터들의 게이트가 접속된 노드를 통하여 대응되는 상기 컬럼선택신호가 인가됨을 특징으로 하는 반도체 메모리 장치.The semiconductor memory device of claim 2, wherein the corresponding column select signal is applied through a node to which gates of the second NMOS transistors connected between two bit lines adjacent to the memory cells are connected. 제1항에 있어서, 상기 제1수단은 상기 비트라인들과의 전원전압 사이에 채널들이 직렬로 제1피모오스 트랜지스터들을 가지고, 상기 제2수단은 상기 비트라인들 사이에 채널이 직렬로 접속된 제2피모오스 트랜지스터들을 가짐을 특징으로 하는 반도체 메모리 장치.2. The apparatus of claim 1, wherein the first means has first PMOS transistors in series between power supply voltages with the bit lines, and the second means has channels connected in series between the bit lines. And a second PMOS transistor. 제5항에 있어서, 상기 제1피모오스 트랜지스터들의 게이트는 인접한 메모리 셀들에 인가되는 컬럼선택신호의 상보신호가 접속됨을 특징으로 하는 반도체 메모리 장치.The semiconductor memory device of claim 5, wherein the gates of the first PMOS transistors are connected with complementary signals of column select signals applied to adjacent memory cells. 제5항에 있어서, 상기 메모리 셀들에 인접한 두 비트라인 사이에 접속된 상기 제2피모오스 트랜지스터들의 게이트가 접속된 노드를 통하여 상기 컬럼선택신호가 인가됨을 특징으로 하는 반도체 메모리 장치.6. The semiconductor memory device of claim 5, wherein the column select signal is applied through a node to which gates of the second PMOS transistors connected between two bit lines adjacent to the memory cells are connected. ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is to be disclosed based on the initial application.
KR1019950028401A 1995-08-31 1995-08-31 Semiconductor memory device with reduced bit line coupling KR100192569B1 (en)

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KR1019950028401A KR100192569B1 (en) 1995-08-31 1995-08-31 Semiconductor memory device with reduced bit line coupling

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Application Number Priority Date Filing Date Title
KR1019950028401A KR100192569B1 (en) 1995-08-31 1995-08-31 Semiconductor memory device with reduced bit line coupling

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KR970012748A true KR970012748A (en) 1997-03-29
KR100192569B1 KR100192569B1 (en) 1999-06-15

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