KR970012174A

KR970012174A - Ablation circuit

Info

Publication number: KR970012174A
Application number: KR1019950025005A
Authority: KR
Inventors: 윤성희
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-08-14
Filing date: 1995-08-14
Publication date: 1997-03-29
Also published as: KR0150159B1

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

아비트레이션 회로.Arbitration circuit.

2. 발명에 해결하려고 하는 기술적 과제2. Technical problem to be solved in invention

외부에서 플렉시블하게 중재를 할 수 있게 하는 회로를 제공한다.Provides a circuit that enables flexible arbitration from the outside.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

개선된 아비트레이션 회로는 외부에서 인가되는 데이타를 라이트 신호에 따라 저장하고 이를 변경우선 선택신호로서 출력하는 레지스터 부와 상기 변경우선 선택신호에 응답하여 다수개의 리퀘스트 입력신호들을 우선 순서대로 재구성하고 이를 변경 리퀘스트 입력신호들로서 출력하는 제1멀티플렉서와, 상기 변경 리퀘스트 입력신호들을 게이팅하여 미리 설정된 우선순위에 따라 하나씩 응답된 출력신호를 제공하는 중재부와 상기 중재부의 출력신호들을 차례로 출력하는 제2멀티플렉서를 포함한다.The improved abitation circuit reconfigures a plurality of request input signals in order in response to the change priority selection signal and a register unit that stores externally applied data according to a write signal and outputs it as a change priority selection signal. A first multiplexer for outputting as request input signals, an arbitration section for outputting the output signals replied one by one according to a preset priority by gating the change request input signals, and a second multiplexer for outputting the output signals of the arbitration section in turn. do.

4. 발명의 중요한 용도4. Important uses of the invention

전자 디바이스의 중재회로로서 사용된다.It is used as an arbitration circuit of an electronic device.

Description

Ablation circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 아비트레이션 회로 블록도,1 is an ablation circuit block diagram of the present invention;

제2도는 제1도에 따른 구체 회로도,2 is a detailed circuit diagram according to FIG.

제3도는 제2도에 따른 각부의 출력 타이밍도.3 is an output timing diagram of each part according to FIG. 2;

Claims

In the arbitration circuit, a register unit for storing externally applied data according to a write signal and outputting the data as a change priority selection signal and a plurality of request input signals are reconstructed in order in response to the change priority selection signal first, and the change request is performed. A first multiplexer for outputting as input signals, an arbitration unit gating the change request input signals and providing output signals responsive to each other according to a preset priority, and an output signal of the arbitration unit corresponding to the request input signals; And a second multiplexer for sequentially outputting the arbitration signals.

In the arbitration circuit, for changing the arbitration condition flexibly, selection means for storing externally applied data according to a setting signal and outputting it as a selection line, and a logic state of the change priority selection signal. First multiplexing means for outputting a plurality of request input signals as change request input signals in response; An arbitration unit for gating the change request input signals and providing output signals replied one by one according to a predetermined fixed priority, and receiving output signals of the arbitration unit and outputting arbitration signals corresponding to the request input signals in order. And a multiplexing means.

3. The abitation circuit according to claim 2, wherein said selecting means consists of two flip-flops.

4. The arbitration circuit according to claim 3, wherein said first and second multiplexing means each comprise four four to one multiplexers.

※ Note: The disclosure is based on the initial application.