KR970011684B1 - Cdma mobile system - Google Patents

Abstract

a first decoder receiving a first chip selection signal generated in a selector and transcoding interface board assembly(SXIA); a second decoder receiving a second chip selection signal generated in a selector and transcoding board assembly(SXOA); a dual memory which outputs a first and second BUSY signal controlling the direction of data transmission by receiving the signals generated in the first and second decoder, and transmits the stored data in the set transmission direction; a first operation control part controlling the operation of SXIA according to the bus signal generated in SXIA and the signal generated in the first decoder and the first BUSY signal generated in the dual memory; and a second operation control part controlling the operation of SXOA according to the bus signal generated in SXOA and the signal generated in the second decoder and the second BUSY signal generated in the dual memory.

Description

Control circuit for dual port RAM communication in vocoder / selector of CDMA mobile communication control station

1 is a block diagram of a control circuit for dual port RAM communication in a vocoder / selector according to the present invention.

2 is a diagram illustrating the main operation timing of FIG.

The present invention provides a selector and transcoding interface board assembly (hereinafter referred to as SXIA) and a selector and transcoding board assembly located in a transcoding and selecting bank (TSB) block located in a control station of a mobile communication system. Dual port RAM is used for communication between the SXIA and SXOA to reduce data loss and increase the data transmission efficiency in the vocoder / selector of the CDMA mobile communication control station. It relates to a control circuit for.

In general, data communication between the SXIA and the SXOA has conventionally used respective communication lines. However, in order to connect a plurality of SXOAs to one SXIA, transmission data is lost due to the complexity of the entire circuit, i.e., each SXOA is individually separated. Because of this problem, data collision occurs at the SXIA receiving the data, which reduces the communication performance.

An object of the present invention for solving the above problems is to use the selector interface unit and the selector unit using a dual port RAM for communication between the selector interface unit and the selector interface located in the TSB block located in the control station of the mobile communication system The present invention provides a control circuit for dual port RAM communication in a vocoder / selector of a CDMA mobile communication control station to reduce transmission data loss therebetween and increase data transmission efficiency.

A feature of the present invention for achieving the above object is a control device for data communication between a selector interface and a selector interface located in a TSB block existing in a control station of a mobile communication system. A first decoder receiving a chip selection signal, a second decoder receiving a second chip selection signal generated by the selector unit, a signal generated by the first decoder and a signal generated by the second decoder And a dual memory for outputting first and second busy signals for controlling the data transmission direction and transmitting the stored data in a predetermined transmission direction, a bus signal generated from the selector interface unit and a first signal generated from the first decoder. A first controlling the operation of the selector interface unit according to a signal and a first visa signal generated in the dual memory According to the operation control section and the second busy signal been generated in the signal and the dual memory is generated at the bus signal and the second decoder is generated from the selector unit is in a second operation control unit for controlling an operation of the selector unit.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a configuration diagram of a control circuit for dual port RAM communication in a vocoder / selector according to the present invention, which increases communication performance between the two modules and enables multiple SXOA connections to one SIXA. .

It consists of four dual ports RAM between SXIA and SXOA to enable byte, word, and word operation.

In addition, data communication uses the interrupt method, which is inherent to the dual port RAM.

In dual port RAM, when two independent ports approach the same cell, the BUSY * signal is asserted toward the later of the two ports.

Since the detection of the BUSY signal is already occupying the cell to be accessed to another port, wait for the other port to release and end the cycle.

Access timing uses J-K F / F to control dual port ram read and write timing.

The CS * signal is generated at the decoder U2 when the SXIA accesses the dual port RAM.

This signal and AS * signal are input to the preset pin of J-K F / F of U4 via AND gate and inverter.

This way, the J-K F / F preset pin will always be high (H) when the SXIA has dual port ram access.

As shown in FIG. 1, the SXIA latches the occurrence of BUSY * when the dual port RAM approaches.

As shown in Fig. 1, the dual port ram light cycle timing is performed after a certain time (delay CS * signal for a certain time: Ta) when the dual port ram is selected. If AS * signal is negated, DSACK * signal is checked and if it is not asserted, DSACK * signal is generated. If AS * signal is negated, DSACK * signal is also negated and cycle ends.

In the case of an address competition when accessing the dual port RAM, the BUSY * signal is generated after MAX 20ns after the chip select signal is asserted, so the delay time for the BUSY * check is Tb shown in Figure 2.

Tb is a delay time for valid data of the light port to be input after the BUSY signal is negated.

When the BUSY * signal occurs during the read cycle, the dual port ram read cycle generates the DASCK signal after the time Tb for valid data output after BUSY is negated as shown in Figure 1.

The operation of the control circuit for dual port RAM communication in the vocoder / selector of the CDMA mobile communication control station performing the above operation will be described in detail with reference to FIG.

First of all, the process of saving data from SXIA to SXOA's dual port RAM is the same as comparing the highest address of the bus provided by SXAI with the BDID (board ID signal) signal provided by the backplane, and the AS provided by SXIA as a bus. The * and CS * signals open the doors of the data buffer and address buffer.

The direction of the buffer is then determined with the WR * signal (in this case Low) sent from the SXIA to the bus.

Using the CS * signal and A0 and A1, a dual port RAM having a required size among the long word ports is selected.

The DSACK * signal sent to the SXIA generates the DSACK * signal after a sufficient delay in consideration of the collision of the dual port RAM as described above.

If the DSACK * signal is not generated properly, system performance may be degraded.

The SXOA ends the cycle when the AS * signal from the SXIA is negated.

The process of reading data from SXIA to SXOA's dual port RAM is the same as comparing the highest address of the bus provided by SXIA with the BDID (board ID signal) signal provided by the backplane, and the AS provided by SXIA as a bus. The * and CS * signals open the doors of the data buffer and address buffer.

The direction of the buffer is determined with the WR * signal (in this case High) sent from the SXIA to the bus.

At this time, the CS * (dual port ram select signal) signal is used to generate the BUSY * signal as described above.

The DSACK * signal generation to the SXIA floats the DSACK * signal in consideration of the collision of the dual port RAM as described above.

After that, when the AS * signal from SXIA is negated, the cycle is terminated.

By providing a control circuit for dual port RAM communication in a vocoder / selector of a CDMA mobile communication control station according to the present invention operating as described above, it reduces communication data loss between the selector and the selector interface in the mobile communication and reduces communication performance. This makes it possible to have more vocoder interfaces in one selector.

Claims (1)

CLAIMS 1. A control apparatus for data communication between a selector interface unit and a selector unit located in a TSB block existing in a control station of a mobile communication system, comprising: a first decoder for receiving a first chip selection signal generated by the selector interface unit; A second decoder configured to receive a second chip selection signal generated by the selector; Dual memory for receiving the signal generated from the first decoder and the signal generated from the second decoder to output the first and second busy signals for controlling the data transmission direction and to transmit the stored data in the set transmission direction A first operation control unit controlling an operation of the selector interface unit according to a bus signal generated from the selector interface unit, a signal generated from the first decoder, and a first busy signal generated from the dual memory; And a second operation controller configured to control an operation of the selector according to a bus signal generated by the selector, a signal generated by the second decoder, and a second busy signal generated by the dual memory. Control circuit for dual port RAM communication in the vocoder / selector of a mobile communication control station.