KR970011647B1 - Formation method of gate oxide for semiconductor - Google Patents
Formation method of gate oxide for semiconductor Download PDFInfo
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- KR970011647B1 KR970011647B1 KR1019940005772A KR19940005772A KR970011647B1 KR 970011647 B1 KR970011647 B1 KR 970011647B1 KR 1019940005772 A KR1019940005772 A KR 1019940005772A KR 19940005772 A KR19940005772 A KR 19940005772A KR 970011647 B1 KR970011647 B1 KR 970011647B1
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- oxide film
- process tube
- stream generating
- generating part
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000012495 reaction gas Substances 0.000 claims abstract description 16
- 239000007789 gas Substances 0.000 claims abstract description 5
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 230000008016 vaporization Effects 0.000 claims description 4
- 101100076847 Oryza sativa subsp. japonica MFT2 gene Proteins 0.000 abstract description 6
- 101100345757 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) MMT2 gene Proteins 0.000 abstract description 6
- 239000012159 carrier gas Substances 0.000 abstract description 5
- 238000006243 chemical reaction Methods 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 101100345756 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) MMT1 gene Proteins 0.000 abstract 2
- 101150020463 mft1 gene Proteins 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000005496 eutectics Effects 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
제1도는 산화막을 증착하기 위한 산화막 증착기의 개략도.1 is a schematic diagram of an oxide film depositor for depositing an oxide film.
제2도는 종래의 산화막 증착을 위한 제조 공정도,2 is a manufacturing process diagram for conventional oxide film deposition,
제3도는 본 발명에 따른 산화막 증착을 위한 제조 공정도.3 is a manufacturing process diagram for oxide film deposition according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반응개스 형성부,2 : 스트립 발생부,1: reaction gas forming part, 2: strip generating part,
3 : 공정튜브,4 : 히팅블럭,3: process tube, 4: heating block,
5 : 써머커플5: Thermocouple
본 발명의 균일도 및 두께조절이 용이한 반도체 소자의 게이트 산화막 형성 방법에 관한 것이다.The present invention relates to a method for forming a gate oxide film of a semiconductor device in which uniformity and thickness can be easily adjusted.
일반적으로, 게이트 산화막은 고집적 소자의 집적도에 따라 더욱 얇어지게 됨에 따라 이에 상응하는 산화막의 성장 방법이 개발되어야 한다.In general, as the gate oxide becomes thinner according to the degree of integration of the highly integrated device, a method of growing the corresponding oxide film needs to be developed.
종래의 게이트 산화막 형성 방법을 제1도를 통하여 상세히 살펴보면 다음과 같다.A conventional method of forming a gate oxide film will now be described in detail with reference to FIG. 1.
먼저, 제1도는 증착 시키고자 하는 소오스 개스 O와 H, Cl가 포함된 캐리어개스 N를 반응시키는 반응개스 형성부(1)와 반응개스를 증기화하는 스트립(stream) 발생부(2), 그리고, 증기화된 반응개스를 웨이퍼에 증착시키게 되는 공정튜브(3)로 구성되어 있으며, 도면부호 5는 반응개스 형성부(1)의 온도를 측정하는 써머커플을 나타낸다.First, FIG. 1 shows a reaction gas forming unit 1 for reacting a source gas O to be deposited and a carrier gas N including H and Cl, a stream generating unit 2 for vaporizing a reaction gas, and And a process tube 3 for depositing a vaporized reaction gas on a wafer, and reference numeral 5 denotes a thermocouple for measuring the temperature of the reaction gas forming unit 1.
만약 700℃에서 웨이퍼에 반응개스를 증착시키려 할 때는 공정튜브(3)를 700℃에 세팅(setting)시키게 된다. 그리고, 허팅브럭(4)에 의해 900℃의 온도를 유지하는 반응개스 형성부(1)에서 형성된 반응개스는 스트림 발생부(2)로 옮겨져 웨이퍼가 놓인 공정튜브(3)에 주입되게 증착되게 된다.If the reaction gas is to be deposited on the wafer at 700 ° C., the process tube 3 is set at 700 ° C. Then, the reaction gas formed in the reaction gas forming unit 1 maintaining the temperature of 900 ° C. by the Herting block 4 is transferred to the stream generating unit 2 and deposited to be injected into the process tube 3 on which the wafer is placed. .
온도 조절 방법을 더욱 구체적으로 살펴보면, 웨이퍼에 산화막을 증착하기 전에 공정조건을 적정한 수준으로 세팅(setting)하는 스탠드 바이 상태를 이루는 스탠드 바이 상태시 스트림 발생부의 온도는 800℃이고, 공정튜브의 3지역 즉, MFT1(Main Furnace Temperature 1), MFT2, MFT3의 온도는 각각 650℃, 650℃, 650℃ 정도를 유지하게 되어 있다. 그리고, 웨이퍼에 산화막이 증착되는 주산화 공정에서는 스트림 발생부의 온도는 900℃이고, 제2도에 도시된 바와 같이 공정튜브의 MFT1, MFT2, MFT3 온도는 각각 700 내지 800℃ 정도를 유지하게 된다. 또한 증착후의 열처리 공정온도는 900℃에서 행해진다.In more detail, the temperature control method has a temperature of the stream generating unit in the stand-by state of forming a stand-by state in which the process conditions are set to an appropriate level before depositing an oxide film on the wafer, and the temperature of the stream generator is 800 ° C. That is, the temperatures of MFT1 (Main Furnace Temperature 1), MFT2, and MFT3 are maintained at about 650 ° C, 650 ° C, and 650 ° C, respectively. In the main oxidation process in which the oxide film is deposited on the wafer, the temperature of the stream generating unit is 900 ° C., and MFT1, MFT2, and MFT3 temperatures of the process tube are maintained at about 700 to 800 ° C., respectively, as shown in FIG. In addition, the heat processing process temperature after vapor deposition is performed at 900 degreeC.
그러므로, 흡열 반응에 의해 형성되는 반응개스의 열손실을 고려하여 900℃의 온도에서 형성된 반응개스는 공정튜브에 주입될 때의 온도가 약 800℃가 되어 700℃의 저온 산화를 공정튜브에서 진행하더라도 800℃에서 산화막을 증착하는 효과가 발생하게 됨으로써 산화막의 균일도가 떨어지는 문제점이 발생하여 왔다.Therefore, in consideration of the heat loss of the reaction gas formed by the endothermic reaction, the reaction gas formed at the temperature of 900 ° C. becomes about 800 ° C. when the temperature is injected into the process tube, and the low temperature oxidation of 700 ° C. proceeds in the process tube. As the effect of depositing an oxide film at 800 ° C. has occurred, a problem of inferior uniformity of the oxide film has occurred.
따라서, 상기 문제점을 해결하기 위하여 안출된 본 발명은 공정튜브와 스트림 발생부와의 온도 편차를 줄여 웨이퍼 상에 형성되는 산화막의 두께 조절 및 균일도가 높은 산화막을 형성함으로써 반도체 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 게이트 산화막 형성 방법을 제공하는데 그 목적이 있다.Therefore, the present invention devised to solve the above problems is to reduce the temperature variation between the process tube and the stream generating unit to improve the electrical properties of the semiconductor device by forming an oxide film having a high thickness and uniformity of the oxide film formed on the wafer. It is an object of the present invention to provide a method for forming a gate oxide film of a semiconductor device.
상기 목적을 달성하기 위하여 본 발명은, 웨이퍼에 산화막을 증착하기 전에 공정조건을 적정한 수준으로 세팅(setting)하는 스탠드 바이 상태를 이루고, 공정튜브에 놓인 웨이퍼 상에 산화막을 증착하게 되는 주산화 단계를 포함하여 이루어지는 반도체 소자의 게이트 산화막 형성방법에 있어서, 상기 스탠드 바이 상태시 소오스 개스를 반응시켜 반응된 반응개스를 증기화하는 스트림 발생부의 온도는 730 내지 770℃로 하고, 공정튜브내의 온도를 640 내지 660℃로 유지하는 단계 ; 상기 주산화 공정시 상기 스트림 발생부의 온도는 750 내지 780℃로 유지시키고, 공정 튜브의 온도를 690 내지 710℃ 정도를 유지하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a main oxidation step in which the oxide film is deposited on a wafer placed in a process tube in a stand-by state that sets process conditions to an appropriate level before depositing an oxide film on a wafer. In the method for forming a gate oxide film of a semiconductor device comprising a, the temperature of the stream generating unit for vaporizing the reaction gas by reacting the source gas in the stand-by state is 730 to 770 ℃, the temperature in the process tube is 640 to Maintaining at 660 ° C .; The temperature of the stream generating unit during the main oxidation process is characterized in that it comprises a step of maintaining at a temperature of 750 to 780 ℃, maintaining the temperature of the process tube of about 690 to 710 ℃.
이하, 첨부된 도면 제3도를 통하여 본 발명에 따른 일실시예를 상세히 설명한다.Hereinafter, an embodiment according to the present invention will be described in detail with reference to FIG. 3.
먼저, 본 발명은 제3도에 도시된 바와 같이 주산화 및 열처리 온도를 변화하는 것이다.First, the present invention is to change the main oxidation and heat treatment temperature as shown in FIG.
즉, 스탠드 바이 상태시 스트림 발생부의 온도는 730 내지 770℃로 하고, 공정튜브의 MFT1, MFT2, MFT3의 온도는 각각을 640 내지 660℃로 유지한다. 그리고 주산화 공정에서는 스트림 발생부의 온도는 750 내지 780℃로 유지시켜 소오스 개스 O와, H, Cl기가 포함된 캐리어개스 N의 흡열반응으로 생성된 반응개스가 스트림 발생부에서 700℃ 정도를 유지하도록 하며, 제3도에 도시된 바와 같이 공정튜브의 MFT1, MFT2, MFT3 온도는 각각 690 내지 710℃ 정도를 유지하게 한다. 또한 증착후의 열처리 공정온도는 830 내지 870℃에서 행한다. 이때 스트림 발생부의 온도가 750 내지 780℃이고 공정튜브 내로 주입되는 반응개스의 온도(700℃)가 차이가 있는 것은 주산화 공정시 H2와 O2및 N2캐리어 개스로 반응시킬 경우 반응초기에는 발열반응에 의해 스트림 발생부의 온도가 상승하나 H2와 O2및 N2캐리어 개스에 의해 생성된 증기에 의해 스트림 발생부의 온도가 50 내지 80℃ 정도 하강되므로 결국 계속적인 주 산화 공정시 스트림 발생부의 온도와 공정 튜브의 온도가 거의 같게 된다.That is, in the stand-by state, the temperature of the stream generator is 730 to 770 ° C, and the temperatures of the MFT1, MFT2 and MFT3 of the process tube are maintained at 640 to 660 ° C, respectively. In the main oxidation process, the temperature of the stream generating unit is maintained at 750 to 780 ° C so that the reaction gas generated by endothermic reaction of the source gas O and the carrier gas N containing H and Cl groups is maintained at about 700 ° C in the stream generating unit. As shown in FIG. 3, MFT1, MFT2, and MFT3 temperatures of the process tubes are maintained at about 690 to 710 ° C, respectively. In addition, the heat processing process temperature after vapor deposition is performed at 830-870 degreeC. In this case, the temperature of the stream generating unit is 750 to 780 ° C and the temperature of the reaction gas injected into the process tube (700 ° C) is different. When reacting with H 2 , O 2 and N 2 carrier gas during the main oxidation process, The exothermic reaction raises the temperature of the stream generator, but the steam generated by the H 2 and O 2 and N 2 carrier gases lowers the temperature of the stream generator by 50 to 80 ° C. The temperature and the temperature of the process tube are about the same.
상기와 같이 이루어지는 본 발명은 반응개스를 증기화시키는 스트림 발생부와 웨이퍼 상에 산화막이 형성되는 공정 튜브와의 온도차를 최소화하여 산화막 두께 조절 및 산화막 질을 균일하게 형성할 수 있어 고집적 반도체 소자의 전기적 특성을 향상시킬 수 있는 효과가 있다.The present invention made as described above can minimize the temperature difference between the stream generating unit for vaporizing the reaction gas and the process tube in which the oxide film is formed on the wafer to control the thickness of the oxide film and to form the oxide film uniformly, thereby the electrical characteristics of the highly integrated semiconductor device. There is an effect to improve.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940005772A KR970011647B1 (en) | 1994-03-22 | 1994-03-22 | Formation method of gate oxide for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940005772A KR970011647B1 (en) | 1994-03-22 | 1994-03-22 | Formation method of gate oxide for semiconductor |
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| Publication Number | Publication Date |
|---|---|
| KR950027911A KR950027911A (en) | 1995-10-18 |
| KR970011647B1 true KR970011647B1 (en) | 1997-07-12 |
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| KR1019940005772A KR970011647B1 (en) | 1994-03-22 | 1994-03-22 | Formation method of gate oxide for semiconductor |
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| KR950027911A (en) | 1995-10-18 |
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