KR950027911A - Gate oxide film formation method of a semiconductor device - Google Patents

Gate oxide film formation method of a semiconductor device Download PDF

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Publication number
KR950027911A
KR950027911A KR1019940005772A KR19940005772A KR950027911A KR 950027911 A KR950027911 A KR 950027911A KR 1019940005772 A KR1019940005772 A KR 1019940005772A KR 19940005772 A KR19940005772 A KR 19940005772A KR 950027911 A KR950027911 A KR 950027911A
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KR
South Korea
Prior art keywords
oxide film
temperature
maintaining
process tube
wafer
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Application number
KR1019940005772A
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Korean (ko)
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KR970011647B1 (en
Inventor
엄금용
Original Assignee
김주용
현대전자산업주식회사
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Priority to KR1019940005772A priority Critical patent/KR970011647B1/en
Publication of KR950027911A publication Critical patent/KR950027911A/en
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Publication of KR970011647B1 publication Critical patent/KR970011647B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 웨이퍼에 산화막을 증착하기 전에 공정조건을 적정한 수준으로 세팅(setting)하는 스탠드 바이 상태를 이루고, 공정튜브에 놓인 웨이퍼상에 산화막을 증착하게 되는 주산화 단계를 포함하여 이루어지는 반도체 소자의 게이트 산화막 형성방법에 있어서, 상기 스탠드 바이 상태시 소오스 개스를 반응시켜 반응된 반응개스를 증기화 하는 스트립 발생부의 온도는 730 내지 770℃로 하고, 공정튜브내의 온도를 640 내지 660℃도로 유지하는 단계; 상기 주산화 공정시 상기 스트림 발생부의 온도 750 내지 780℃로 유지시키고, 공정튜브의 온도를 690 내지 710℃정도를 유지하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성방법에 관한 것으로, 반응개스를 증기화 하는 스트림 발생부와 웨이퍼 상에 산화막이 형성되는 공정 튜브와의 온도차를 최소화 하여 산화막 두께 조절 및 산화막 질을 균일하게 형성할 수 있어 고집적 반도체 소자의 전기적 특성을 향상 시킬 수 있는 효과가 있다.The present invention comprises a main oxidation step of forming a stand-by state for setting process conditions to an appropriate level before depositing an oxide film on a wafer and depositing an oxide film on a wafer placed in a process tube. In the oxide film forming method, the temperature of the strip generating unit for vaporizing the reaction gas by reacting the source gas in the stand-by state is 730 to 770 ℃, maintaining the temperature in the process tube 640 to 660 ℃; It relates to a method of forming a gate oxide film of a semiconductor device comprising the step of maintaining the temperature of the stream generating unit in the main oxidation process at 750 to 780 ℃, maintaining the temperature of the process tube of about 690 to 710 ℃. By minimizing the temperature difference between the stream generator that vaporizes the reaction gas and the process tube where the oxide film is formed on the wafer, the thickness of the oxide film can be controlled and the oxide film quality can be uniformly formed. It works.

Description

반도체 소자의 게이트 층간절연막 형성방법Method of forming gate interlayer insulating film of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 산화막 증착을 위한 제조 공정도.3 is a manufacturing process diagram for oxide film deposition according to the present invention.

Claims (2)

웨이퍼에 산화막을 증착하기 전에 공정조건을 적정한 수준으로 세팅(setting)하는 스탠드 바이 상태를 이루고, 공정튜브에 놓인 웨이퍼상에 산화막을 증착하게 되는 주산화 단계를 포함하여 이루어 지는 반도체 소자의게이트 산화막 형성방법에 있어서, 상기 스탠드 바이 상태시 소오스 개스를 반응시켜 반응된 반응개스를 증기화하는 스트림 발생부의 온도는 730내지 770℃로 하고, 공정튜브내의 온도를 640내지 660℃도로 유지하는 단계; 상기 주산화 공정시 상기 스트림 발생부의 온도는 750 내지 780℃로 유지시키고, 공정튜브의 온도를 690 내지 710℃정도를 유지하는 단계를 포함하여 이루어 지는 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성방법.Forming a gate oxide film of a semiconductor device comprising a main oxidation step of forming a stand-by state in which process conditions are set to an appropriate level before depositing an oxide film on a wafer, and depositing an oxide film on a wafer placed in a process tube. The method of claim 1, wherein the temperature of the stream generating unit for vaporizing the reaction gas by reacting the source gas in the stand-by state is 730 to 770 ℃, maintaining the temperature in the process tube to 640 to 660 ℃; And maintaining the temperature of the stream generating unit at 750 to 780 ° C. and maintaining the temperature of the process tube at about 690 to 710 ° C. during the main oxidation process. 제1항에 있어서, 주산화 단계후 형성된 산화막을 830 내지 870℃에서 열처리하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성방법.The method of claim 1, further comprising heat-treating the oxide film formed after the main oxidation step at 830 to 870 ° C. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940005772A 1994-03-22 1994-03-22 Formation method of gate oxide for semiconductor KR970011647B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940005772A KR970011647B1 (en) 1994-03-22 1994-03-22 Formation method of gate oxide for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940005772A KR970011647B1 (en) 1994-03-22 1994-03-22 Formation method of gate oxide for semiconductor

Publications (2)

Publication Number Publication Date
KR950027911A true KR950027911A (en) 1995-10-18
KR970011647B1 KR970011647B1 (en) 1997-07-12

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Application Number Title Priority Date Filing Date
KR1019940005772A KR970011647B1 (en) 1994-03-22 1994-03-22 Formation method of gate oxide for semiconductor

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Publication number Publication date
KR970011647B1 (en) 1997-07-12

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