KR970010683B1 - Semiconductor device & manufacturing method - Google Patents

Abstract

A semiconductor memory device using SOI includes a first semiconductor substrate, a plurality of semiconductor layers formed on the first semiconductor substrate and divided from one another by a first insulating layer, a conductive pattern formed on sidewalls of the semiconductor layers, a gate electrode of a transistor, which is formed on the semiconductor layers and serves as a word line, a first contact hole formed on the first insulating layer placed on the semiconductor layers through the back side of the substrate, and a capacitor formed on the semiconductor layers and connected to the conductive pattern through the first contact hole, through the back of the semiconductor substrate.

Description

Semiconductor memory device using SOI and manufacturing method

1 is a cross-sectional view of a DRAM cell manufactured by a conventional method.

2 is a cross-sectional view of a DRAM cell produced by the present invention.

3 is a perspective view of a DRAM cell produced by the present invention.

4 through 12 are plan and cross-sectional views illustrating a method of manufacturing a DRAM cell according to the present invention.

* Explanation of symbols for main parts of the drawings

10: first semiconductor substrate l2: insulating film

13a: conductive pattern 14: first insulating layer

16, 17, 18: storage electrode, dielectric film, plate electrode 19: second insulating layer

20: second semiconductor substrate 21: gate insulating film

22: gate electrode 23: impurity region

26: bit line BC: first contact hole

H: 2nd contact hole

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a DRAM (Dynamic Random Access Memory) cell using a silicon-oxide-insulator (SOI) and a method of manufacturing the same.

In order to increase the degree of integration of semiconductor memory cells, especially DRAM cells, it is important to integrate as many devices as possible in a minimum area.

Since 256 Mb and IGb class DRAM cells have an area of 0.3 μm ² or less in a memory cell composed of one transistor and one capacitor, a three-dimensional cell structure is required to overcome the limitation of the area. Lateral You need to change from layout to vertical layout structure.

In 1992, Toshiyuki Nishihara et al. Proposed a memory cell structure using SOI (Reference: IEDM '92, A Buried Capacitor DRAM Cell with bonded SOI for 256M and 1Gbit DRAMs).

1 is a cross-sectional view of the BC cell proposed in the above document, wherein reference numeral 100 denotes a silicon layer, reference numeral 120 denotes an isolation region, reference numeral 140 a capacitor, reference numeral 160 a capacitor contact region, and reference numeral 180 a wordline. The gate electrode of the transistor provided by FIG.

As shown in FIG. 1, the BC cell may maximize the area of the capacitor because the capacitor 140 is completely buried under the silicon layer 100. However, in order to form the contact region 160 connecting the capacitor 140 and the transistor, a silicon layer (reference numeral T) having a predetermined thickness or less, for example, 80 nm thick, must be left, and thus, if the silicon layer is too thin, It is difficult to secure. In addition, since the contact region 160 is formed by an ion implantation process separate from diffusion from polycrystalline silicon doped with impurities used as a storage electrode of the capacitor, a contact point (J) of the contact region is formed. There is a difficulty in controlling the diffusion so that only the edge of the word line 180 is reached. If the diffusion proceeds excessively, the electrical characteristics of the transistor may be affected, and the threshold voltage may be greatly changed by the slight misalignment of the formation of the word line 180.

In addition, in order to compensate for the large step of the silicon pillar during the manufacturing process of the BC cell, the area A indicated by the dotted line in FIG. 1 is formed as a dummy, which is not efficient in terms of design.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of stabilizing the characteristics of a transistor by suppressing diffusion of a capacitor contact region.

In addition, another object of the present invention is to provide a production method suitable for achieving the above object.

In order to achieve the above object, the saw has a first semiconductor substrate; A plurality of semiconductor layers formed on the first semiconductor substrate, each of which is separated by a first insulating layer, and a conductive pattern formed on sidewalls of the semiconductor layers; A gate electrode of the transistor formed on the semiconductor layer and provided as a word line; A first contact hole formed in a first insulating layer on the semiconductor layer on a rear surface of the first semiconductor substrate; And a capacitor formed on the rear surface of the first semiconductor substrate and connected to the conductive pattern through the first contact hole.

According to a preferred embodiment of the present invention, the semiconductor layer is formed in a square shape and does not require a separate contact hole region for connecting the capacitor and the transistor. In addition, a first impurity region of a transistor connected to the capacitor through the conductive pattern is formed on one side of the upper semiconductor layer, and a second impurity region is formed on the surface of the semiconductor layer between the gate electrodes.

In order to achieve the above object, the present invention provides a semiconductor device comprising: a first step of forming a plurality of semiconductor layers on a first semiconductor substrate and forming a conductive pattern on sidewalls of the semiconductor layers; A second step of forming a first insulating layer on the resultant; A third step of exposing the conductive pattern by forming a first contact hole in a first insulating layer on the semiconductor layer; Forming a capacitor connected to the conductive pattern on the first insulating layer; Bonding a second semiconductor substrate to the capacitor via a second insulating layer; And a sixth step of etching the back surface of the first semiconductor substrate.

According to a preferred embodiment of the present invention, the semiconductor layer is a step of etching a first trench in the main region of the first semiconductor substrate in a first direction, the second semiconductor substrate perpendicular to the first direction Etching the second trench in the direction to form the semiconductor layer.

The present invention connects the capacitor and the transistor by a conductive pattern formed on the sidewall of the semiconductor layer. Therefore, since a separate diffusion process for forming a capacitor contact region is not necessary, electrical characteristics of the transistor can be stabilized.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a cross-sectional view of a DRAM cell produced by the present invention, and FIG. 3 is a perspective view of a DRAM cell provided by the present invention.

2 and 3, a plurality of semiconductor layers formed by trench etching the first semiconductor substrate, each separated by the first insulating layer 14, that is, the sidewalls of the active regions 10 are conductive. A pattern 13a is formed, and an insulating spacer 12 is formed between the conductive pattern 13a and the active region 10. In this case, the conductive pattern 13a is formed to extend to an upper portion of the active region 10 (which becomes a lower portion in the figure), and serves as a contact region for connecting a capacitor and a transistor.

On the back surface of the first semiconductor substrate (below in the figure), a first contact hole (not shown) for connecting a capacitor to a transistor is provided in the first insulating layer 14 on the active region 10. And a capacitor including a strip electrode 16, a dielectric film monovalent and a plate electrode 18 connected to the conductive pattern 13a through the first contact hole. A new second semiconductor organ 20 is formed on the capacitor via a second insulating layer 19. All the elements constituting the semiconductor memory device are formed on the first semiconductor substrate. The second semiconductor substrate 20 is provided to serve as a support for the devices.

On the upper surface of the first semiconductor substrate (the upper portion in the figure), a gate electrode 22 of the transistor is formed on the active region 10 via a gate insulating film 21. The gate electrode 22 is provided as a word line. A source region 23 of the transistor is formed on one side of the upper portion of the active region 10, and a drain region 23 ′ of the transistor is formed on the surface of the active region 10 between the gate electrodes 22. have. The source region 23 is connected to the storage electrode 16 through the conductive pattern 13a. The bit line 26 is formed on the gate electrode 22 via the third insulating layer 24, and the bit line 26 is formed in the second contact hole H formed in the third insulating layer 26. It is connected to the drain region 23 'through.

4 through 12 are plan and cross-sectional views illustrating a method of manufacturing a DRAM cell according to the present invention.

4 is a plan view showing an active region defined by the first trench T1, and FIG. 5 is a cross-sectional view taken along the cutting line BB 'of FIG. 4, and the first trench T1, the insulating film 12, and the conductive layer. A step of forming 13 is shown. A photoresist is applied on the first semiconductor substrate 10, and the photoresist is exposed and developed to form a first photoresist pattern (not shown) in a line shape in the Y-axis direction on a plane. Subsequently, the first semiconductor substrate 10 is etched to a depth of about 2,000 μs using the first photoresist pattern as a mask to form a first trench T1, thereby defining a plurality of active regions separated only in the X-axis direction. do. Here, the depth of the first trench T1 is determined according to the thickness of the active region to be left, and preferably, the depth of the first trench T1 is 2,000 Å or less. Subsequently, the first photoresist pattern is removed, and an insulating film, such as an oxide film, is formed on the entire surface of the resultant to a thickness of about 110 Å by a thermal oxidation process. T1) The insulating film 12 on the inner wall is left for separation of the contact region to be formed later. Subsequently, the substrate 10 is etched to a depth of about 200 μs again using the insulating film 12 as a mask, and then, for example, polysilicon doped with impurities is deposited to a thickness of about 500 μs on the entire surface of the resultant conductive layer ( 13).

FIG. 6 is a plan view showing an active region and a conductive pattern 13a formed by the second trench T2, and FIG. 7 is a cross-sectional view taken along the cutting line XX 'of FIG. 6, and the conductive pattern 13a and the second pattern. A step of forming two trenches T2 is shown. By patterning the conductive layer by performing a photolithography process on the entire surface of the resultant layer on which the conductive layer (reference numeral 13 of FIG. 5) is formed, along the sidewalls of the active regions separated only in the X-direction by the first trench T1. A conductive pattern (not shown) is formed. In this case, the conductive pattern is patterned to extend to a predetermined portion above the active region. Subsequently, a photoresist is applied to the entire surface of the resultant, and the photoresist is exposed and developed to form a second photoresist pattern (not shown) in a line shape in the X-axis direction. Next, the second trench T2 is formed by etching the conductive pattern and the first semiconductor substrate 10 to a depth of about 2,000 mV using the second photoresist pattern as a mask. As a result, a plurality of active regions separated in both X and Y directions are obtained, and the conductive pattern 13a is separated in units of each active region. In this case, the conductive pattern 13a is connected to the conductive patterns of adjacent cells under the first and second trenches T1 and T2. The conductive pattern 13a is used as a contact region for connecting a storage electrode of a capacitor to be formed later and a source region of the transistor, and a first contact hole BC for the contact is formed thereon in a subsequent process. Therefore, according to the present embodiment, since the active region does not require a separate contact hole region for connecting the storage electrode, the active region may be formed in a square shape.

In general, in order to manufacture a DRAM that is highly integrated at 256 Mb or more, a resolution of 0.3 μm or less is required and a sub-half micron pattern must be formed. When the photoresist is formed in a square pattern, it is difficult to form a fine pattern due to the interference of the light source and the process margin is very small. This problem can be solved by forming the photoresist in a line and space pattern. Therefore, according to the present embodiment, the size of the active region can be further reduced by forming the photoresist in a line and space pattern and performing two trench etchings separately. In addition, since the conductive patterns used as the contact regions are etched together when the second trenches are formed, the active patterns may be easily separated from each active region.

FIG. 8 is a plan view of the region C in which the capacitor is to be formed, and FIG. 9 and FIG. 12 are cross-sectional views taken along the cutting peak DD 'of FIG.

9 illustrates forming the first insulating layer 14 and the first contact hole BC. The first insulating layer 14 is formed by depositing an oxide by a chemical vapor deposition method or applying spin-on-glass (SOG) to a thickness of 5,000 GPa or more on the entire surface of the resultant region in which the active region and the conductive pattern l3a are formed. Form. In this case, the first insulating layer l4 is formed to have a predetermined thickness with respect to the active region while completely filling the first and second trenches. When the stepped surface of the first insulating layer 14 is severely formed by the lower structures, the surface of the first insulating layer 14 is planarized by a conventional chemical mechanical polishing (CMP) method. Subsequently, by etching a predetermined portion of the first insulating layer 14 by a photolithography process, a first contact hole BC exposing the conductive pattern 13a is formed.

10 illustrates forming a capacitor. The storage electrode 16 of the capacitor is formed on the entire surface of the product in which the first contact hole is formed. Subsequently, a high dielectric material is deposited on the entire surface of the storage electrode 16 to form a dielectric film 17, and then a conductive material is deposited on the dielectric film 17 to form a plate electrode 18. This process completes the stack capacitor. Here, the shape of the storage electrode may be adjusted according to the capacitance of the desired capacitor, and in the subsequent SOI process, the height of the storage electrode may be increased without a step problem because the capacitor is completely buried under the active region.

FIG. 11 shows forming the second insulating layer 109 and the second semiconductor substrate 20. As shown in FIG. The second insulating layer 19 is formed by depositing an insulating material, for example, an oxide, on the plate electrode 18 of the capacitor to a thickness of several thousand micrometers or more by chemical vapor deposition, and then, using the CMP method, the second insulating layer ( Planarize the surface of 19). Subsequently, a second semiconductor substrate 20 is formed by bonding a new wafer onto the planarized second insulating layer 19 by a direct wafer bonding method. Next, after the back surface of the first semiconductor substrate is turned upside down, the back lap method and the CMP method are successively performed to etch the back surface. The etching process proceeds until the active regions 10 are separated from each other by the first insulating layer 14. At this time, the conductive patterns 13a connected to the conductive patterns of adjacent cells are separated from each other under the first and second trenches.

12 illustrates forming transistors and bit lines 26. A thermal oxidation process is performed on the back surface of the etched first semiconductor substrate to form a gate insulating film 21 on the active region 10, and then polysilicon doped with conductive materials, such as impurities, is formed on the entire surface of the resultant substrate. Deposit. Subsequently, the polysilicon is patterned by a photolithography process to form the gate electrode 22, and then ion implantation is performed on the entire surface of the resultant to form source and drain regions 23 and 23 'of the transistor. The source region 23 is formed on one side of the upper portion of the active region 10, and is connected to the storage electrode 16 of the capacitor through the conductive pattern 13a. The drain region 23 ′ is formed on the surface of the active region 10 between the gate electrodes 22. As a material constituting the gate electrode 22, a structure in which polycrystalline silicon or polycrystalline silicon and tungsten silicide (WSix) are not stacked with impurities may be used. Subsequently, an insulating material is deposited on the entire surface of the resultant to form a third insulating layer 24, and then a predetermined portion of the third insulating layer 24 is etched by a photolithography process to expose the drain region 23 ′. A second contact hole (not shown) is formed. Next, a conductive material is deposited on the entire surface of the resultant and patterned by a photolithography process to form a bit line 26 connected to the drain region 23 ′ through the second contact hole.

As described above, the present invention connects the capacitor and the transistor by using the conductive pattern formed on the side of the active region as the capacitor contact region. Therefore, since a separate diffusion process for forming a capacitor contact region is not necessary, electrical characteristics of the transistor can be stabilized. In addition, since the silicon layer is not formed to be thin for the contact region of the capacitor as in the related art, the process is much easier and the active region can be formed in the forward direction, thereby increasing the integration degree of the semiconductor memory device.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (12)

A first semiconductor substrate; A plurality of semiconductor layers formed on the first semiconductor substrate, each of which is separated by a first insulating layer; A conductive pattern formed on sidewalls of the semiconductor layer; A gate electrode of the transistor formed on the semiconductor layer and provided as a word line; A first contact hole formed in a first insulating layer on the semiconductor layer on a rear surface of the first semiconductor substrate; And a capacitor formed on the back surface of the first semiconductor substrate, the capacitor being connected to the conductive pattern through the first contact hole. The semiconductor memory device of claim 1, wherein the semiconductor layer is formed in a square shape. The semiconductor memory device of claim 1, wherein the capacitor is buried under the semiconductor layer. The semiconductor memory device of claim 1, further comprising an insulating film formed between the conductive pattern and the semiconductor layer. The semiconductor memory device of claim 1, further comprising a first impurity region formed on one side of the semiconductor layer and connected to the capacitor through the conductive pattern. The semiconductor memory device of claim 1, further comprising a second impurity region formed on a surface of the semiconductor layer between the gate electrodes. 7. The semiconductor memory device of claim 6, further comprising a bit line formed to be connected to the third insulating layer and the second impurity region formed on the gate electrode. Forming a plurality of semiconductor layers on the first semiconductor substrate and forming a conductive pattern on sidewalls of the semiconductor layers; A second step of forming a first insulating layer on the resultant; A third step of exposing the conductive pattern by forming a first contact layer example first contact hole on the semiconductor layer; Forming a capacitor connected to the conductive pattern on the first insulating layer; Bonding a second semiconductor organ to the capacitor via a second insulating layer; And a sixth step of etching the back surface of the first semiconductor substrate. The method of claim 8, wherein the semiconductor layer comprises: etching a first trench of a main region of the first semiconductor substrate in a first direction; And etching the first semiconductor substrate in a second trench in a second direction perpendicular to the first direction to form a semiconductor layer. The method of claim 8, wherein etching the back surface of the first semiconductor substrate is performed until the semiconductor layers are separated from each other by the first insulating layer. 9. The method of claim 8, further comprising planarizing the surface of the insulating layer in the fifth step. The semiconductor of claim 8, further comprising forming a transistor on the semiconductor layer on the rear surface of the first semiconductor substrate by a conventional method after the sixth step of etching the rear surface of the first semiconductor substrate. Method of manufacturing a memory device.