KR0150987B1 - Dram capacitor & its manufacturing method - Google Patents

Abstract

A memory device in which BC and DC are formed above and below the active region, respectively, and a manufacturing method thereof are described. The first storage region may include a bit line and word lines positioned in an upper or lower direction of the first active region, a first storage electrode contact window formed in the first active region in a direction in which the word lines are located. And a second storage electrode contact window and a bit line contact window formed in the first active region in the direction in which the bit line is located. Therefore, the gap between DC or BC and the gate electrode suitable for 1G class DRAM can be secured, and the cell capacitance can be easily increased.

Description

DRAM device having capacitor divided into upper and lower parts and manufacturing method thereof

1 is a layout diagram according to a conventional method for manufacturing a DRAM.

FIG. 2 is a cross-sectional view illustrating DRAM fabrication using the layout diagram of FIG. 1.

3 is a cross-sectional view showing a DRAM device manufactured according to an embodiment of the present invention.

4 is a layout diagram according to an embodiment of the present invention for DRAM manufacturing.

5A to 5F are layout views laid out in a process order to manufacture a DRAM device according to an embodiment of the present invention.

6A to 6I are cross-sectional views illustrating a method of manufacturing a DRAM according to an exemplary embodiment of the present invention, taken along line VI-VI of FIGS. 5A to 5F.

7A to 7I are cross-sectional views illustrating a method of manufacturing a DRAM device according to an exemplary embodiment of the present disclosure, taken along line VII-VII of FIGS. 5A to 5F.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a DRAM device having a capacitor that is divided into upper and lower portions in which a word line or a bit line is formed on or below a active region, respectively. will be.

As the integration of DRAM devices increases, the size of cells has been reduced by about one third for each generation. This means that the cell size has been reduced as a means for integrating a plurality of cells in a small area. Each generation of DRAM has grown fourfold, including 4M, 16M, 64M, 256M, and 1G, but since the cell size has been reduced by only one-third, the chip has grown slightly.

In this trend, the cell size of 1G DRAM is expected to be reduced to about 0.3μm ~ 0.25μm 2. This means that the cell is only about the size of a cell contact window of 16M DRAM. Even at this small size, conventional DRAMs have one gate electrode (word line), one BC (Buried Contact) and half DC (Direct Contacr) for each cell. A contact window for connecting the phosphorus and the drain), and the cell capacitance has to satisfy about 30 fF / cell.

In conventional DRAM cells, BC, DC, and word lines are all over the active region, so that their process margins (gaps to prevent shorts between the conductive lines) become very small. In the case of 16M DRAM, the gap between DC or BC and wordline is 0.2μm ~ 0.25μm, but it is expected to be reduced to less than 500GHz at 1G DRAM level, which is a big problem for Giga-class DRAM. This is because such a process margin makes the process impossible.

This problem has been a problem since 64M DRAM, and one way to solve this problem is to form a pad of polysilicon in BC or DC, and then form a storage electrode or bit line connected to the top of the pad. The method was adopted. At this time, BC or DC is usually formed in a self-aligning method, which causes a problem of shortening the distance between the pad and the edge of the word line.

Such a problem of reducing the gap between the gate electrode and another conductive material layer not only deteriorates the electrical characteristics of the memory device, but also seriously makes the manufacturer of the memory device impossible. Is urgent.

FIG. 1 is a layout diagram according to a conventional method for manufacturing a DRAM, and shows an arrangement relationship between an active region, a word line, and BC and DC.

In the layout diagram of FIG. 1, the region defined by the dashed line is the mask pattern 1 for the active region, the region defined by the dashed line is the mask pattern 2 for the word line, and the region defined by the solid line is BC. Is the mask pattern 3 for the region, and the region defined by the short dotted line is the mask pattern 4 for the DC. At this time, the interval L between the mask pattern 2 for the word line and DC or BC is only about 500 mW in 1G DRAM.

FIG. 2 is a cross-sectional view illustrating a DRAM device manufactured using the layout diagram of FIG. 1, wherein reference numeral 10 denotes a semiconductor substrate, 12, 18 and 26 an insulating layer, 14 an active region, and 16 a gate electrode. 20 denotes a source / drain, 22 a pad, 24 a bit line, 28 a storage electrode, 30 a dielectric film, and 32 a plate electrode. At this time, the distance L between the gate electrode 16 and the pad 22 corresponds to the distance L between the mask pattern 2 and the mask patterns 3 and 4 in FIG. 1. The spacing between the edge of 16 and the pad 22 is indicated by M.

Referring to FIG. 2, it can be seen that as described above, the distance between the gate electrode 16 and the pad 22, the edges of the gate electrode, and the pad may decrease gradually as the degree of integration of the memory device increases. .

Accordingly, an object of the present invention is to provide a DRAM device having capacitors that are divided up and down to widen the distance between a word line and BC or DC.

Another object of the present invention is to provide a DRAM device having capacitors divided into upper and lower parts which can be formed by dividing word lines and bit lines into upper and lower portions of an active region.

It is still another object of the present invention to provide a DRAM device having capacitors separated up and down which can easily increase cell capacitance.

Still another object of the present invention is to provide a preferable manufacturing method for manufacturing the DRAM device.

The objects of the present invention are a first active region, a bit line and word lines positioned respectively in an upper or lower direction of the first active region, and a first active region formed in the first active region in a direction in which the word lines are located. DRAM having a storage electrode contact window, a second storage electrode contact window formed in the first active region in the direction in which the bit line is located, and a bit line contact window; Achieved by the device.

In a preferred embodiment, the word lines are formed under the first active region, the bit lines are formed over the first active region, and are formed in the active region through the second storage electrode contact window. The second storage electrode connected to the source is connected to the source through a bit line formed under the second storage electrode. In the bit line, a spacer for insulating the second storage electrode is formed at a portion through which the second storage electrode passes.

The word lines have a form in which a first word line, a second word line, a third word line, and a fourth word line are arranged in sequence, wherein the first word line is closest to the first storage electrode contact window. It is arranged to be located. Only a gate oxide layer is formed under the first word line and the third word line, and an insulating layer is formed under the second word line and the fourth word line.

In the first active area, when the length of the direction (horizontal direction) in which the contact windows are arranged in sequence is 1 pitch, the first direction in the longitudinal direction based on the first active area. The second active regions are arranged in a form shifted in the horizontal direction by about a quarter pitch with respect to the active regions, and the first active regions and the second active regions are regularly arranged throughout the memory cell region.

In this case, the second active region is a form in which the first active region is inverted by 180 °.

In another preferred embodiment, the word line is formed above the first active region, and the bit line is formed below the first active region.

Still another object of the present invention is to provide a first process for forming a first active region on a first substrate through a first insulating film, and a second process for forming first and second gate electrodes on the first active region. And a third process of forming a second insulating film on the entire surface of the resultant, a fourth process of forming a first storage electrode contact window at an edge of the first active region adjacent to the first gate electrode, and contacting the first storage electrode. A fifth process of forming a first capacitor connected to a source of the transistor formed in the first active region through the window; the resultant is inverted, and then the first insulating layer on the drain of the transistor is removed from the first active region A sixth step of forming a bit line contact window, a seventh step of forming a bit line connecting to the drain through the bit line contact window, an eighth step of forming a third insulating film on the entire surface of the resultant, and Forming a second storage electrode contact window at an edge portion of the first active region adjacent to the second gate electrode and forming a second capacitor connected to the source of the transistor through the second storage electrode contact window; It is achieved by a method for manufacturing a DRAM device having a capacitor separated up and down, comprising a tenth step.

Preferably, after the first step, forming a fourth insulating film on the entire surface of the resultant, removing the fourth insulating film formed on the region where the first and second gate electrodes are to be formed, and the entire surface of the resultant. In addition, a process of forming a gate oxide film may be further added.

More preferably, the second storage electrode contact window is formed to pass through the bit line. In this case, after the ninth process, a process of forming a spacer on the sidewall of the second storage electrode contact window is added.

Bit lines and word lines are formed on or below the active area, respectively, and first storage electrode contact windows are formed in the active area where the word lines are formed, and active in the direction in which the bit lines are formed. By forming a second storage electrode contact window and a bit line contact window in the region, and forming a word line and a bit line on the upper portion of the active region, both the first and second storage electrode contact window and the bit line contact window are formed in the active region. Compared to the conventional method formed on the top, the distance between the contact windows and the word line can be made much larger. Therefore, the degree of integration of the semiconductor memory device can be reliably increased.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

In one embodiment of the present invention, the bit line and the second storage electrode are formed above the active region and the word line and the first storage electrode are formed below the active region. At this time, the active region is formed by introducing a silicon on insulator (SOI) method, as described in the article A Buried Capacitor DRAM Cell with Bonded SOI for 256M and 1Gbit DRAMs (invented by Toshiyuki Nishihara, et al.), 1993, published in IEDM. It is mentioned in detail in an article published in the IEDM issue of ULSI DRAM / SIMOX with Stacked Capacitor Cells for Low-Voltage Operation (T.Eimori, et al.).

In the former paper, the method of reducing the cell step by forming a capacitor in the lower portion of the active region by introducing the SOI method is mentioned, and in the latter paper, it is formed by introducing the SOI method using a separation by IMplanted OXygen (SIMOX). A method of forming a capacitor on the semiconductor layer after separating the semiconductor layer into unit active regions will be described.

However, according to the invention mentioned in the former paper, the cell step can be reduced, but since the cell capacitors are formed at the lower part of the active region, problems such as ensuring sufficient cell capacitance and spacing between gate electrodes of DC or BC are required. Can not be solved. In addition, according to the invention mentioned in the latter paper, the semiconductor layer can be effectively separated by the SIMOX method, but this has the inverse effect of reducing the cell capacitance, which is not easy to apply to the integrated DRAM device.

The present invention solves all the problems of the invention mentioned in the former and the latter papers, by forming a cell capacitor alternately on the upper and lower portions of the active region to facilitate the increase of the cell capacitance, bit line and word line By forming the upper and lower portions of the active region, respectively, the gap between the gate electrode and DC or BC can be sufficiently secured.

3 is a cross-sectional view illustrating a DRAM device manufactured according to an exemplary embodiment of the present invention, wherein reference numerals 42, 45, 52, 62, and 68 are insulating films, 44 are active regions, 47 are gate oxide films, and 48 are A gate electrode, that is, a word line, 50a is a first source for connecting the first storage electrode, 50b is a drain, 50c is a second source for connecting the second storage electrode, 56 is a first storage electrode, and 58 is A first dielectric layer, 60 a first plate electrode, 64 a second substrate, 66 a bitline, 72 a spacer, 74 a second storage electrode, 76 a second dielectric film and 78 a second Plate electrode is shown.

According to the cross-sectional view of FIG. 3, a word line 48 is formed below the active region 44 and a bit line 66 is formed thereon. The first storage electrode 56 is connected to the first source 50a through a first storage electrode contact window 54 (hereinafter referred to as a first BC) formed at one edge of the active region. The second story electrode 74 is connected to the second source 50c through a second storage electrode contact window 70 (hereinafter referred to as a second BC) formed at the other edge of the active region, The line 66 is connected to the drain 50b through a bit line contact window (indicated by A) (hereinafter referred to as DC) formed in the central portion of the active region. In this case, the first BC is formed below the active region 44, and the second BC and DC are formed above the active region.

The second BC is formed through the bit line, and a spacer 72 made of an insulating film is formed therein.

The gate oxide film 47 is formed only under the gate electrode used in each active region (in FIG. 3, the even-numbered gate electrode with reference to the left side), and the gate oxide film 47 below the other gate electrode. ) And the insulating film 45 are laminated. This is to avoid forming a parasitic capacitor between the other gate electrode and the active region.

The shape of the area occupied by the storage electrode is that the first storage electrode 56 is separated in units of cells, and the transverse direction of the active area (in the third figure, the left (or right) to the right (or left) direction). The second storage electrode 74 is separated in units of cells, and has a rectangular shape close to a square centered on each second BC.

4 is a layout diagram according to an embodiment of the present invention for manufacturing a DRAM, in which a region defined by a dashed line is a mask pattern 5 for an active region, and a region defined by dotted lines is formed below the active region. The mask patterns 6 and 7 for the display are shown, and the region defined by the solid line indicates the mask patterns 8 and 9 for the structure formed on the active area. In this case, the mask pattern 6 is for the gate electrode, that is, the word line, 7 is for the first BC, 8 is for DC, and 9 is for the second BC.

Of the mask patterns 6 for the gate electrode, the wider one (the even number when referring to the left side of FIG. 4) is the gate electrode used in each active region, and the other is the other active region ( Specifically, the gate electrode is used in the active region disposed in the longitudinal direction of the active region.

When comparing the mask patterns of FIGS. 1 and 4, the distance between BC and DC and the gate electrode of FIG. 4 is almost equal to the distance between BC and DC and the gate electrode of FIG. It can be seen that it is two to three times wider.

5A to 5F are layout views laid out in a process order to manufacture a DRAM device according to an embodiment of the present invention.

5A shows a mask pattern for forming an active region, where reference numeral 100 is for a first active region and 102 is for a second active region.

In this case, the second active region is disposed in the longitudinal direction of the first active region, and when the horizontal length of the first active region is 1 pitch, the second active region is disposed by moving about 1/4 pitch in the vertical direction.

FIG. 5B shows a mask pattern for forming the gate electrode, the first BC and the gate oxide film open, wherein reference numeral 110 is for opening the gate oxide film, 112 is for the gate electrode, and 114 is the first electrode. It is for BC.

At this time, only the mask pattern 112 (the width of which is relatively wide) disposed at an odd number with respect to the mask pattern 114 for forming the first BC is a mask pattern for forming the gate electrode used in each active region. And others are mask patterns for forming gate electrodes used in neighboring active regions. The mask pattern 110 is disposed to intersect with the mask pattern arranged in the odd numbered number.

Alternatively, in one embodiment of the present invention, the mask patterns disposed in the second active region are disposed 180 ° out of phase with respect to the mask patterns disposed in the first active region.

FIG. 5C illustrates a mask pattern 120 for forming the first storage electrode. The mask pattern 120 is formed to have a long rectangular shape in the horizontal direction with the mask pattern 114 at the center thereof, and the width (length in the vertical direction). ) Corresponds to the width of the active area.

5d shows a mask pattern for DC and bit line formation, where reference numeral 130 is for DC and 132 is for bit line.

The mask pattern 132 is formed in a long band shape in the horizontal direction, and its width is widened in the regions A and B where DC and the second BC are to be formed. In particular, the area B in which the second BC is to be formed is larger than in the area A in which the DC is to be formed. Since the said area B is arrange | positioned mutually staggered across the cell array part with reference to FIG. 5d, process margin can fully be ensured. This is possible because the phases of the mask pattern disposed in the first active region and the mask pattern disposed in the second active region are reversed by about 180 degrees.

In general, in order to form a folded bitline, a mask pattern for forming a bit line is disposed between the active regions (between the mask pattern 100 and the mask pattern 102 in FIG. 5D), The line is extended only to the DC region to connect the bit line and the drain. However, in an embodiment of the present invention, as shown in the mask pattern 132, the mask pattern 132 for forming the bit line is disposed to be included in the mask patterns 100 and 102 for forming the active region.

5E illustrates a mask pattern 140 for forming a second BC, and is disposed to be included in a region B of the mask pattern 132.

FIG. 5F illustrates a mask pattern 150 for forming the second storage electrode, and is formed in a rectangular shape close to a square with respect to the mask pattern 140.

5A to 5F, the mask patterns illustrated in FIGS. 5B and 5C are formed under the first and second active regions formed by the mask patterns 100 and 102. The mask pattern shown in FIGS. 5d to 5f is for a structure formed on the active region.

As described in FIG. 4, according to the layout diagram according to an embodiment of the present invention, it can be seen that the distance between BC and DC and the gate electrode is much larger than that in the memory device manufactured by the conventional method. .

Hereinafter, a manufacturing method according to an embodiment of the present invention will be described with reference to FIGS. 6A to 6I and 7A to 7I.

6a to 6i are cross-sectional views illustrating a method of manufacturing a DRAM device according to an embodiment of the present invention, taken along line VI-VI of FIGS. 5a to 5f, by process, and FIGS. 7a to 7i. 5A to 5F are cross-sectional views illustrating a method of manufacturing a DRAM device according to an embodiment of the present invention, taken along line VII-VII of FIG. 5A to FIG. 5F.

First, referring to FIGS. 6A and 7A, a process of forming the first insulating film 42 and the semiconductor layer 44a is illustrated, which is, for example, SiO ₂ or the like on the entire surface of the first substrate 40. A first step of forming the first insulating film 42 by forming the same insulating material in a thickness of about 1,000 kPa to 10,000 kPa, and a thickness of about 500 kPa to 2,000 kPa of the semiconductor layer 44a on the first insulating film. Silicon On Insulator (SOI) is grown to a second process.

Referring to FIGS. 6B and 7B, a process of separating the semiconductor layer into each active region unit is illustrated, and FIG. 5A is a cut line VI-VI and VII-VII.

For example, the active layer 44 and the device may be separated by dividing the semiconductor layer into each active region using a device isolation method such as the SIMOX (Separation by IMplanted Oxygen) method introduced in the above-mentioned paper (T.Eimori et al.). The process of forming the separator 46 is performed.

6C and 7C, a process of forming the gate electrode 46, the impurity diffusion region 50, the second insulating film 52, and the first BC 54 is illustrated in FIG. 5B. Lines VI-VI and VII-VII are cut out.

This is a first process of forming a second insulating film 45 on the entire surface of the resultant active region, a second process of performing an etching process using the mask pattern 110 and using the second insulating film as an etching target, A third step of forming a gate oxide film 47 on the entire surface of the resultant, a fourth step of forming a gate electrode 48 by performing an etching process using the mask pattern 112 after forming a conductive material layer on the resultant, A fifth process of forming an impurity layer 50 in the active region by performing an impurity implantation process in which the gate electrode 48 is implanted and prevented from masking; and a sixth process of forming an insulating material on the entire surface of the resultant to form a third insulating film 52. The etching process using the mask pattern 114 is performed, and the process proceeds to a seventh process of forming the first BC 54 exposing one edge of the active region.

In this case, the second insulating film 45 is formed by applying an insulating material such as silicon nitride film (SiN) to a thickness of about 100 kPa to 300 kPa, preferably 200 kPa, and the gate oxide film 47 is formed. The conductive material layer is formed of a thickness of about 50 kPa to about 200 kPa, for example, a polysilicon material such as about 500 kPa to about 2,000 kPa, preferably about 1,500 kPa, and the third insulating film ( 52) is formed by applying an insulating material such as BPSG (Boro-Phosphorus-Silicate Glass) to a thickness of about 1,000 kPa to 5,000 kPa, preferably to a thickness of 3,000 kPa, and the first BC (54) The impurity layer formed at one edge of the active region exposed to the surface becomes the first source 50a.

6C and 7C, the gate oxide film 47 is formed only under the gate electrode (the odd-numbered gate electrode with respect to the first BC) having a relatively wide width, which is a gate having a relatively narrow width. This is because the electrode is a gate electrode which is not used in the active region 44. When only the gate oxide film is formed below the gate electrode having a relatively narrow width, the gate oxide film acts as a dielectric film of the capacitor by the gate electrode and the bit line during the operation of the bit line (formed in a later process). Because it forms. Therefore, in this embodiment, the gate oxide film is formed only under the gate electrode having a relatively wide width.

6D and 7D illustrate a process of forming a first capacitor including the first storage electrode 56, the first dielectric layer 58, and the first plate electrode 60, and the VI of FIG. 5C. -VI and VII-VII lines are cut out.

The conductive material layer is formed on the entire surface of the resultant material on which the first BC is formed, and then, by using the mask pattern 120 and performing the etching process using the first conductive material layer as an etching target, the cells are separated into cell units. A first process of forming the first storage electrode 56, a second process of forming the first dielectric layer 58 on the entire surface of the first storage electrode 56, and forming a second conductive material layer on the entire surface of the resulting product. A third process of forming the first plate electrode 60 and a fourth process of planarizing the upper portion of the first plate electrode 60 are performed.

In this case, the first conductive material layer is formed of a conductive material such as polycrystalline silicon, for example, about 500 kPa to about 2,000 kPa, preferably about 1,000 kPa, and the planarizing the upper portion of the first plate electrode. Four steps are performed using the planarization process, such as CMP etc. (chemical-mechanical polypropylene).

As shown in FIG. 6D, the first storage electrodes are formed in one storage electrode area occupied by two cells, that is, in the storage electrode region occupied by two cells, and thus, the first storage electrodes are the same as in the conventional method of forming two storage electrodes in two cells. In the structure, double the cell capacitance can be obtained.

Referring to FIGS. 6E and 7E, a process of forming the fourth insulating layer 62 and the second substrate 64 and a process of removing the first substrate are illustrated. The first process of forming the fourth insulating film 62 on the entire surface of the first plate electrode 60, the second process of adhering the second substrate on the fourth insulating film 62 and the resultant, and then inverting the first substrate. Is removed to proceed to the third process of exposing the first insulating film 42 to the surface.

In this case, the fourth insulating layer 62 is formed of an insulating material such as BPSG, for example, about 500 kV to about 5,000 kPa, preferably about 3,000 kPa, and removes the first substrate. Silver proceeds by processes, such as CMP, for example.

Referring to FIGS. 6F and 7F, the process of forming the DC (A) and the bit line 66 is shown, and the VI-VI and VII-VII lines of FIG. 5D are cut out.

This is performed by forming an electrically conductive material layer on the entire surface of the first process and the resultant by using the mask pattern 130 and performing an etching process using the first insulating film 42 as an etch target and forming DC (A). The etching process using the mask pattern 132 and the conductive material layer as an etching target is performed to form a bit line 66.

At this time, the conductive material layer, for example, a conductive material such as tungsten silicon (WSi _X ) and the like to form a thickness of about 500 kPa ~ 3,000 kPa, preferably about 1,000 kPa.

When the bit line 66 refers to the mask pattern 132, it can be seen that the width of the bit line 66 is widened in the region where the DC and the second BC are to be formed. 7F compares the width of the bit line in the region where the second BC is to be formed with the width of the bit line in the region where the second BC is not formed.

The drain 50b is formed by a process of injecting impurities through the DC before forming the bit line, or after the conductive material layer is formed, impurities contained in the conductive material layer diffuse into the active region. It is formed by the process.

Referring to FIGS. 6G and 7G, a process of forming the second BC 70 is shown, and lines VI-VI and VII-VII of FIG. 5E are cut out.

The first and second insulating layers 68 and 42 may be formed using the first process of forming the fifth insulating layer 68 on the entire surface of the resultant bit line 66 and the mask pattern 140. An etching process using the bit line 66 as an etching target is performed to form a second BC 70 in which the other edge of the active region is exposed.

At this time, the fifth insulating film 68 is formed with an insulating material such as ONO (oxide film / nitride film / oxide film), for example, in a thickness of about 5 kPa to 50 kPa, preferably about 45 kPa. The second BC 70 is formed through the bit line 66, as can be seen with reference to the mask pattern 140.

In addition, after the second process, a process of injecting impurities into the entire surface of the resultant may be added to form a second source 50c connected to the second storage electrode at the other edge of the active region.

Referring to FIGS. 6h and 7h, a process of forming the spacer 72 is shown, which is formed on the entire surface of the resultant on which the second BC is formed, for example, an insulating material such as an oxide film of about 100 kPa to 1,000 kPa. The first process of forming a thickness of about 500 kPa, and anisotropic etching using this insulating material as an etch target on the entire surface of the resultant, leaving the insulating material only on the inner sidewall of the second BC. Is proceeded to the second step of forming ().

At this time, the spacer 72 is to prevent the second storage electrode and the bit line 66 to be formed in a subsequent process.

6I and 7I illustrate a process of forming a second capacitor including the second storage electrode 74, the second dielectric layer 76, and the second plate electrode 78. Lines VI-VI and VII-VII of FIG. 5f are cut out.

The first conductive material layer is formed on the entire surface of the resultant product in which the spacer 72 is formed, and then, the etching process using the mask pattern 150 is performed to form second storage electrodes 74 separated by cell units. In the first process, the second process of forming the second dielectric film 76 on the front of the second storage electrode 74 and the second conductive material layer is formed on the entire surface of the resultant to form the second plate electrode 78 In addition, a third process of completing the first capacitor including the second storage electrode 74, the second dielectric layer 76, and the second plate electrode 78 is performed.

In this case, the first conductive material layer is formed of a conductive material such as polycrystalline silicon, for example, in a thickness of about 500 kPa to 2,000 kPa, preferably about 1,000 kPa, and the second conductive material layer is, for example, polycrystalline. It is formed by depositing a conductive material such as silicon.

The second source 50c may be formed not only in the process of FIG. 7g but also in the process of forming the second storage electrode, which is the same as the principle of forming the drain 50b.

The second storage electrodes are formed one per two cells, that is, in the region where two storage electrodes are to be formed, like the first storage electrode. Therefore, when the structure of the capacitor is the same, it is possible to ensure twice the cell capacitance than the memory device manufactured by the conventional method.

Therefore, according to the present invention, first, word lines and bit lines are formed on and below the active region, respectively, and then only the first BC is formed in the direction in which the word lines are formed. By forming the second BC and the DC in the formed direction, the distance between the DC or BC and the gate electrode can be widened two to three times as compared with the related art. Second, by forming one capacitor per two cells above and below the active region, it is possible to secure twice the cell capacitance as in the prior art.

In one embodiment of the present invention, the word line is formed below the active region and the bit line is formed above the active region, but the process is performed. There is no

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea to which the present invention pertains.

Claims (11)

A first active region in which a first source, a drain, and a second source are formed; A bit line disposed above or below the first active region and connected to the drain; Word lines arranged at an upper portion or a lower portion of the first active region where the bit line is not disposed; A first capacitor formed in a direction in which the word lines are disposed, and including a first storage electrode connected to the first source, a first dielectric layer covering the first storage electrode, and a first plate electrode covering the first dielectric layer ; And a second capacitor formed in a direction in which the bit line is disposed, the second capacitor including a second storage electrode connected to the second source, a dielectric film covering the second storage electrode, and a second plate electrode covering the second dielectric film. DRAM device having a capacitor divided into upper and lower, characterized in that it comprises. The DRAM device of claim 1, wherein the word lines are disposed below the first active region, and the bit lines are disposed above the first active region. The DRAM device of claim 1, wherein the second storage electrode is connected to the second source through the bit line and is connected to the second source. 4. The capacitor of claim 3, wherein a spacer for insulating the second storage electrode and the bit line is formed at a portion of the bit line through which the second storage electrode passes. Having a DRAM device. 2. The first active region of claim 1, wherein when the length of the direction (horizontal direction) in which the first source, the drain, and the second source are sequentially arranged is set to 1 pitch, the first active region is referred to. And the second active region is arranged in the longitudinal direction of the second active region in a form shifted in the horizontal direction by about a quarter pitch with respect to the first active region. The DRAM device of claim 5, wherein the second active region is disposed in a form in which the first active region is inverted by 180 ° out of phase. The DRAM device of claim 1, wherein the word line is disposed above the first active region, and the bit line is disposed below the first active region. Forming an active region on the first substrate via the first insulating film; Forming a gate oxide film on the active region; Forming first and second gate electrodes on a resultant substrate on which the gate oxide film is formed; Forming a second insulating film on the entire surface of the resultant substrate on which the first and second gate electrodes are formed; Forming a first storage electrode contact window exposing the active region on one side of the first gate electrode; Forming a first capacitor connected to the active region through the first storage electrode contact window; Forming a third insulating film on the resultant substrate on which the first capacitor is formed; Adhering a second substrate onto the third insulating film; Inverting the resultant to the process of adhering the second substrate, and then removing the first substrate to expose the first insulating film; Forming a bit line contact window exposing an active region between the first gate electrode and the second gate electrode; Forming a bit line connecting with the active region through the bit line contact window; Forming a fourth insulating film on the entire substrate; Forming a second storage electrode contact window exposing the active region on one side of the second gate electrode; And forming a second capacitor connected to the active region through the second storage electrode contact window. 10. The method of claim 8, wherein before forming the gate oxide layer, an insulating layer is formed over the entire active region, and then the active region is partially exposed by removing the insulating layer in a region where the first and second gate electrodes are to be formed. The method of manufacturing a DRAM device having a capacitor separated up and down, characterized in that the step of adding. The method of claim 8, wherein the second storage electrode contact window is formed to penetrate through the bit line. The DRAM device of claim 10, further comprising: forming a spacer on sidewalls of the second storage electrode contact window after forming the second storage electrode contact window. Manufacturing method.