KR970009294A - Sync signal discrimination device - Google Patents

Sync signal discrimination device Download PDF

Info

Publication number
KR970009294A
KR970009294A KR1019950021462A KR19950021462A KR970009294A KR 970009294 A KR970009294 A KR 970009294A KR 1019950021462 A KR1019950021462 A KR 1019950021462A KR 19950021462 A KR19950021462 A KR 19950021462A KR 970009294 A KR970009294 A KR 970009294A
Authority
KR
South Korea
Prior art keywords
synchronization signal
signal
synchronizing signal
voltage value
synchronizing
Prior art date
Application number
KR1019950021462A
Other languages
Korean (ko)
Other versions
KR0153668B1 (en
Inventor
노수현
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019950021462A priority Critical patent/KR0153668B1/en
Publication of KR970009294A publication Critical patent/KR970009294A/en
Application granted granted Critical
Publication of KR0153668B1 publication Critical patent/KR0153668B1/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/04Synchronising
    • H04N5/08Separation of synchronising signals from picture signals
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/10Plc systems
    • G05B2219/15Plc structure of the system
    • G05B2219/15049Timer, counter, clock-calendar, flip-flop as peripheral

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)
  • Television Systems (AREA)

Abstract

본 발명은 동기 신호 판별 장치에 관한 것으로서, 입력된 동기 신호를 소정의 레벨 까지 증폭시키는 동기 신호 증폭부(10)와; 증폭된 동기 신호의 전압치를 일정한 레벨의 직류 전압치로 적분하는 동기 신호 적분부(20); 및 적분된 동기 신호의 전압치가 “하이”인 경우에는 3치 동기 신호이고 “로우”인 경우에는 2치 동기 신호임을 판별해내는 동기 신호 판별부(30)로 구성되어 있으며, 상기와 같이 구성된 본 발명은 2치 동기 신호와 3치 동기 신호를 판별해내므로써 각 신호를올바르게 디스플레이하여 HDTV의 3치 동기 신호가 실려 있는 영상 신호인 경우에는 고화질의 영상을 디스플레이하고, 현행의 2치 동기 신호가 실려 있는 영상 신호인 경우에는 일반 영상을 디스플레이 해준다.The present invention relates to a synchronization signal discrimination apparatus, comprising: a synchronization signal amplifier (10) for amplifying an input synchronization signal to a predetermined level; A synchronization signal integrating unit 20 for integrating the voltage value of the amplified synchronization signal into a DC voltage value of a constant level; And a synchronizing signal discrimination unit 30 for discriminating a tri-level synchronizing signal when the integrated synchronizing signal voltage value is "high" and a binary synchronizing signal when "low". According to the present invention, the binary synchronization signal and the three-value synchronization signal are discriminated, and the respective signals are displayed correctly. In the case of the video signal containing the three-value synchronization signal of the HDTV, the high-quality image is displayed, and the current binary synchronization signal is displayed. In case of a video signal, a normal video is displayed.

Description

동기 신호 판별 장치Sync signal discrimination device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 동기 신호 판별 장치에 대한 블럭도.3 is a block diagram of a synchronization signal discrimination apparatus according to the present invention.

Claims (2)

입력된 동기 신호를 소정의 레벨 까지 증폭시키는 동기 신호 증폭부(10)와; 상기 동기 신호 증폭부(10)에서 증폭된 동기 신호의 전압치를 일정한 레벨의 직류 전압치로 적분하는 동기 신호 적분부(20); 및 상기 동기 신호 적분부(30)에서 적분된 동기 신호의 전압치가 “하이” 인 경우에는 3치 동기 신호이고, “로우” 인 경우에는 2치 동기 신호임을 판별해내는 동기 신호 판별부(30)로 구성된 동기 신호 판별 장치.A synchronization signal amplifier 10 for amplifying the input synchronization signal to a predetermined level; A synchronization signal integrating unit 20 for integrating the voltage value of the synchronization signal amplified by the synchronization signal amplifying unit 10 to a DC voltage value having a predetermined level; And a synchronizing signal discrimination unit 30 that determines that the synchronizing signal integrated by the synchronizing signal integrating unit 30 is a triangular synchronizing signal when the voltage value of the synchronizing signal is "high" and a binary synchronizing signal when "low". Synchronization signal determination device composed of. 제1항에 있어서, 상기 동기 신호 적분부(20)가 상기 동기 신호 증폭부(10)에서 증폭된 동기 신호를 정류하여 양의 전압치 만을 출력하는 다이오드(22)와 정류된 동기 신호를 직류 전압치로 적분하는 저항(23)과 콘덴서(24)가 직병렬로 연결된 구조로 이루어져 있는 동기 신호 판별 장치.The method of claim 1, wherein the synchronizing signal integrating unit 20 rectifies the synchronizing signal amplified by the synchronizing signal amplifying unit 10 and outputs only a positive voltage value and the rectified synchronizing signal is a DC voltage. A device for discriminating synchronization signal comprising a structure in which a resistor (23) and a condenser (24) integrated with each other are connected in series and in parallel. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950021462A 1995-07-20 1995-07-20 An apparatus for discriminating synchronizing signal KR0153668B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950021462A KR0153668B1 (en) 1995-07-20 1995-07-20 An apparatus for discriminating synchronizing signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950021462A KR0153668B1 (en) 1995-07-20 1995-07-20 An apparatus for discriminating synchronizing signal

Publications (2)

Publication Number Publication Date
KR970009294A true KR970009294A (en) 1997-02-24
KR0153668B1 KR0153668B1 (en) 1998-11-16

Family

ID=19421114

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950021462A KR0153668B1 (en) 1995-07-20 1995-07-20 An apparatus for discriminating synchronizing signal

Country Status (1)

Country Link
KR (1) KR0153668B1 (en)

Also Published As

Publication number Publication date
KR0153668B1 (en) 1998-11-16

Similar Documents

Publication Publication Date Title
KR910004021A (en) OSD automatic color conversion circuit
KR890006086A (en) Hanging dot reduction device
KR840006586A (en) Automatic Kinescope Bias Control System
KR920001930A (en) Gradation Correction Device and Television Receiver
KR920003742A (en) Video signal average luminance level detection device
KR850007346A (en) Beam Current Control Device
KR920005090A (en) Playback device
KR970009294A (en) Sync signal discrimination device
KR20050031386A (en) Data slicer circuit, integrated circuit and data detection method
EP0369892A3 (en) Dropout detecting circuit
KR920015827A (en) Detector for Telephone Answering Device with Automatic Separation
KR930003086A (en) Video Disc Data Separation Circuit
KR970078675A (en) Color Burst Signal Positioner
KR910004046A (en) Information transmission system using TV luminance signal
KR930005607Y1 (en) Image signal detection circuit of vtr
KR800001740Y1 (en) Automatic gain control apparatus
KR970031816A (en) Synchronization Signal Polarity Recognition Circuit in Multi-Mode Monitors
KR960030192A (en) PALPLUS VRC's Delay Compensation Circuit
KR970057171A (en) Screen processing method during OSD operation in no signal state of television receiver
KR960024864A (en) Monitor's Sync Signal Separation Circuit
JPH07162707A (en) Synchronization separator circuit
KR870006782A (en) Teletext data signal detection circuit
KR910011030A (en) Detection Control Circuit and Method of Image Signal Demodulator
KR970050768A (en) Dropout detection system
KR970023184A (en) Signal-free input processing method of VTR

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010629

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee