KR960024864A - Monitor's Sync Signal Separation Circuit - Google Patents

Monitor's Sync Signal Separation Circuit Download PDF

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Publication number
KR960024864A
KR960024864A KR1019940032706A KR19940032706A KR960024864A KR 960024864 A KR960024864 A KR 960024864A KR 1019940032706 A KR1019940032706 A KR 1019940032706A KR 19940032706 A KR19940032706 A KR 19940032706A KR 960024864 A KR960024864 A KR 960024864A
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KR
South Korea
Prior art keywords
signal
synchronization signal
monitor
synchronizing
separation circuit
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Application number
KR1019940032706A
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Korean (ko)
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KR0122115B1 (en
Inventor
이정욱
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019940032706A priority Critical patent/KR0122115B1/en
Publication of KR960024864A publication Critical patent/KR960024864A/en
Application granted granted Critical
Publication of KR0122115B1 publication Critical patent/KR0122115B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)

Abstract

본 발명은 동기신호 분리회로에 관한 것으로서, 이는 일반적인 컴퓨터 및 산업기기의 모니터에 비디오신호와 동기신호가합성되어 인입될시 모니터 내부에서 비디오신호는 비디오회로에 공급하고 동기신호는 동기회로 및 편향회로에 공급토록동기신호를 분리하도록 하는 것이다.The present invention relates to a synchronizing signal separation circuit, and when a video signal and a synchronizing signal are combined and input to a monitor of a general computer and an industrial device, the video signal is supplied to the video circuit and the synchronizing signal is provided to the synchronizing circuit and the deflection circuit. To isolate the synchronous signal.

특징적인 구성으로는 비디오신호와 동기신호가 복합된 합성신호로부터 동기신호일 때만 온되어 동기신호를 검출하는 동기신호 검출부(10)와, 상기 동기신호 검출부로부터 검출된 동기신호를 일정 레벨 이하로 제어하여 출력하는 동기신호 제어부(20)로 구성함에 있다.As a characteristic configuration, the synchronization signal detection unit 10 which is turned on only when the synchronization signal is a composite signal from the composite signal of the video signal and the synchronization signal and controls the synchronization signal detected by the synchronization signal detection unit to a predetermined level or less, The synchronization signal control unit 20 outputs the same.

Description

모니터의 동기신호 분리회로Monitor's Sync Signal Separation Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 동기분리회로도, 제2도는 본 발명에 의한 동기신호 분리회로도.1 is a conventional synchronous separation circuit diagram, and FIG. 2 is a synchronous signal separation circuit diagram according to the present invention.

Claims (3)

비디오신호와 동기신호가 복합된 합성신호로부터 동기신호 일때만 온되어 동기신호를 검출하는 동기신호검출부(10)와, 상기 동기신호 검출부로부터 검출된 동기신호를 일정 레벨 이하로 제어하여 출력하는 동기신호 제어부(20)로 구성함을 특징으로 하는 모니터의 동기신호 분리회로.The synchronization signal detection unit 10 which is turned on only when the synchronization signal is combined from the composite signal including the video signal and the synchronization signal, detects the synchronization signal, and the synchronization signal which controls and outputs the synchronization signal detected by the synchronization signal detection unit below a predetermined level. The synchronization signal separation circuit of the monitor, characterized in that composed of a control unit (20). 제1항에 있어서, 상기 동기신호 검출부(10)는 정극성인 비디오신호 및 부극성인 동기신호를 입력받는 캐패시터와, 상기 캐패시터에 의해 입력된 부극성 신호인 동기신호에 대해서만 동작하는 트랜지스터와, 부극성 동기신호가 출력단으로 출력되는 것을 방지하는 제너 다이오드로 구성함을 특징으로 하는 모니터의 동기신호 분리회로.2. The synchronizing signal detecting unit (10) according to claim 1, wherein the synchronizing signal detecting unit (10) includes a capacitor which receives a positive video signal and a negative synchronizing signal, a transistor which operates only on a synchronizing signal which is a negative signal input by the capacitor, and A synchronous signal separation circuit of a monitor, characterized by comprising a zener diode that prevents synchronous signals from being output to an output terminal. 제1항에 있어서, 상기 동기신호 제어부(20)는 상기 동기신호 검출부(10)로부터 출력된 정극성 동기신호를입력받는 트랜지스터와, 상기 트랜지스터로부터 출력된 정극성 동기신호의 레벨을 일정 레벨로 유지되도록 하는 제너 다이오드로 구성함을 특징으로 하는 모니터의 동기신호 분리회로.The synchronization signal control unit 20 of claim 1, wherein the synchronization signal control unit 20 maintains the transistors receiving the positive synchronization signal output from the synchronization signal detection unit 10 and the level of the positive synchronization signal output from the transistor at a constant level. A synchronization signal separation circuit of a monitor, characterized by comprising a Zener diode. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940032706A 1994-12-03 1994-12-03 Synchronizing signal KR0122115B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940032706A KR0122115B1 (en) 1994-12-03 1994-12-03 Synchronizing signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940032706A KR0122115B1 (en) 1994-12-03 1994-12-03 Synchronizing signal

Publications (2)

Publication Number Publication Date
KR960024864A true KR960024864A (en) 1996-07-20
KR0122115B1 KR0122115B1 (en) 1997-11-21

Family

ID=19400265

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940032706A KR0122115B1 (en) 1994-12-03 1994-12-03 Synchronizing signal

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KR (1) KR0122115B1 (en)

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Publication number Publication date
KR0122115B1 (en) 1997-11-21

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