KR930013923A - Sequential Switcher System with Frame Switching - Google Patents

Sequential Switcher System with Frame Switching Download PDF

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Publication number
KR930013923A
KR930013923A KR1019910024755A KR910024755A KR930013923A KR 930013923 A KR930013923 A KR 930013923A KR 1019910024755 A KR1019910024755 A KR 1019910024755A KR 910024755 A KR910024755 A KR 910024755A KR 930013923 A KR930013923 A KR 930013923A
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KR
South Korea
Prior art keywords
mux
sync
signal
switcher system
video signal
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Application number
KR1019910024755A
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Korean (ko)
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KR950007831B1 (en
Inventor
김기철
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배순훈
대우전자 주식회사
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Priority to KR1019910024755A priority Critical patent/KR950007831B1/en
Publication of KR930013923A publication Critical patent/KR930013923A/en
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Publication of KR950007831B1 publication Critical patent/KR950007831B1/en

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    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B13/00—Burglar, theft or intruder alarms
    • G08B13/18—Actuation by interference with heat, light, or radiation of shorter wavelength; Actuation by intruding sources of heat, light, or radiation of shorter wavelength

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Studio Circuits (AREA)

Abstract

내용 없음No content

Description

프레임 스위칭기능을 가진 시퀀셜 스위쳐 시스템Sequential Switcher System with Frame Switching

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 시퀀셜 스위쳐 시스템의 블록도이다.1 is a block diagram of a sequential switcher system of the present invention.

제2도는 싱크세퍼레이터의 출력파형도이다.2 is an output waveform diagram of the sink separator.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

2,4,6,8,10 : MUX 12,14,16 : 싱크세퍼레이터2,4,6,8,10: MUX 12,14,16: Sink separator

18 : 모니터 20 : VCR18: monitor 20: VCR

22 : 제어용 마이컴22: control microcomputer

Claims (6)

시퀀셜 스위쳐 시스템에 있어서, 카메라 입력신호를 수신하여 비디오신호를 출력하는 제1MUX(2) ; 제2MUX(4) ; 제3MUX(6) ; 제4MUX(8) ; 제5MUX(10) ; 상기 제1MUX(2)에 연결되어 입력되는 비디오신호에 따라 V. Sync를 생성하는 제1싱크세퍼레이터(12) ; 상기 제2MUX(4)에 연결되어 입력되는 비디오신호에 따라 V. Sync.를 생성하는 제2싱크세퍼레이터(14) ; 상기 제3MUX(6)에 연결되어 입력되는 비디오신호에 따라 V. Sync.를 생성하는 제3싱크세퍼레이터(16) ; 및 상기 제1 내지 제5MUX(2,4,6,8,10)에 각각 제어신호를 출력하여 입력되는 카메라비디오신호를 선택하며, 제1 내지 제3MUX(2,4,6)에 타이머 인터럽트신호를 전송하고 제1 내지 제3싱크세퍼레이터(12,14,16)의 신호를 수신하는 제어용 마이컴(22)으로 구성되며, 제4 내지 제5MUX(8,10)의 출력신호가 각각 모니터 및 VCR에 연결되는 것을 특징으로 하는 시퀀셜 스위쳐 시스템.1. A sequential switcher system comprising: a first MUX (2) for receiving a camera input signal and outputting a video signal; Second MUX 4; Third MUX 6; Fourth MUX 8; Fifth MUX 10; A first sync separator 12 connected to the first MUX 2 to generate V. Sync according to the input video signal; A second sync separator 14 connected to the second MUX 4 to generate a V. Sync. According to the input video signal; A third sync separator (16) connected to the third MUX (6) to generate V. Sync. According to the input video signal; And selecting a camera video signal by outputting a control signal to the first to fifth MUXs (2, 4, 6, 8, and 10), respectively, and a timer interrupt signal to the first to third MUXs (2, 4, 6). And a control microcomputer 22 for transmitting the signals of the first to third sink separators 12, 14 and 16, and output signals of the fourth to fifth MUXs 8 and 10 to the monitor and the VCR, respectively. Sequential switcher system, characterized in that connected. 제1항에 있어서, 상기 제어용 마이컴(22)이 상기 제1싱크세퍼레이터(12)의 V. Sync. 신호를 계수하여 그 결과를 카메라 채널별로 램에 저장하는 것을 특징으로 하는 시퀀셜 스위쳐 시스템.The V. Sync of claim 1, wherein said control microcomputer (22) is configured to control said first sync separator (12). A sequential switcher system, characterized in that the signal is counted and stored in the RAM for each camera channel. 제1항에 있어서, 1초 주기의 정상적인 스위칭동작과 동시에 33.3msec 주기의 고속프레임 스위칭동작을 행하는 것을 특징으로 하는 시퀀셜 스위쳐 시스템.2. The sequential switcher system according to claim 1, wherein a high speed frame switching operation of 33.3 msec periods is performed simultaneously with a normal switching operation of one second period. 제1항에 있어서, 상기 제어용 마이컴(22)이 제1MUX(2)에 130msec 타이머 인터럽트, 제2MUX(4)에 1sec 타이머 인터럽트, 제3MUX(6)에 33.3msec의 타이머 인터럽트신호를 제공하는 것을 특징으로 하는 시퀀셜 스위쳐 시스템.The control microcomputer (22) of claim 1, wherein the control microcomputer (22) provides a 130 msec timer interrupt to the first MUX (2), a 1 sec timer interrupt to the second MUX (4), and a 33.3 msec timer interrupt signal to the third MUX (6). Sequential switcher system. 제1항에 있어서, 상기 제어용 마이컴(22)이 상기 제2싱크세퍼레이터(14)의 V. Sync. 신호를 계수하여 상기 제4MUX(8)의 출력비디오신호를 동기시키는 것을 특징으로 하는 시퀀셜 스위쳐 시스템.The V. Sync of claim 1, wherein said control microcomputer (22) is configured to control said second sync separator (14). And sequential switch to synchronize the output video signal of the fourth MUX (8). 제1항에 있어서, 제4MUX(8)로부터 출력되는 비디오영상의 표시기간이 1sec인 것을 특징으로 하는 시퀀셜 스위쳐 시스템.The sequential switcher system according to claim 1, wherein the display period of the video image output from the fourth MUX (8) is 1 sec. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910024755A 1991-12-27 1991-12-27 Sequential switcher system for frame switching KR950007831B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910024755A KR950007831B1 (en) 1991-12-27 1991-12-27 Sequential switcher system for frame switching

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910024755A KR950007831B1 (en) 1991-12-27 1991-12-27 Sequential switcher system for frame switching

Publications (2)

Publication Number Publication Date
KR930013923A true KR930013923A (en) 1993-07-22
KR950007831B1 KR950007831B1 (en) 1995-07-20

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910024755A KR950007831B1 (en) 1991-12-27 1991-12-27 Sequential switcher system for frame switching

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KR (1) KR950007831B1 (en)

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Publication number Publication date
KR950007831B1 (en) 1995-07-20

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