KR970008891A - Output buffer circuit of semiconductor device - Google Patents

Output buffer circuit of semiconductor device Download PDF

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Publication number
KR970008891A
KR970008891A KR1019950022780A KR19950022780A KR970008891A KR 970008891 A KR970008891 A KR 970008891A KR 1019950022780 A KR1019950022780 A KR 1019950022780A KR 19950022780 A KR19950022780 A KR 19950022780A KR 970008891 A KR970008891 A KR 970008891A
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KR
South Korea
Prior art keywords
gate
output
input
circuit
latch circuit
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Application number
KR1019950022780A
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Korean (ko)
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KR0139859B1 (en
Inventor
최영중
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950022780A priority Critical patent/KR0139859B1/en
Publication of KR970008891A publication Critical patent/KR970008891A/en
Application granted granted Critical
Publication of KR0139859B1 publication Critical patent/KR0139859B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Abstract

본 발명은 반도체 소자의 출력버퍼 회로에 관한 것으로서, 출력 버퍼회로에 크로스커플 래치회로 및 지연회로를 포함하는 2단계 출력 구동회로를 사용하여 출력전압의 빠른 상승 및 하강시의 피크전압을 분산시켜 주므로써 출력버퍼 회로에서 나타나는 정상전류 증가로 인한 잡음 및 접지(ground)전위의 발진(Bouncing)현상을 완화시켜주도록 한 출력버퍼 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit of a semiconductor device, which uses a two-stage output driving circuit including a cross-coupled latch circuit and a delay circuit to disperse the peak voltage during rapid rise and fall of the output voltage. Therefore, the present invention relates to an output buffer circuit that mitigates noise and ground potential oscillation caused by an increase in the steady current present in the output buffer circuit.

Description

반도체 소자의 출력버퍼 회로Output buffer circuit of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 반도체 소자의 출력버퍼 회로도.2 is an output buffer circuit diagram of a semiconductor device according to the present invention.

Claims (4)

전원 및 접지간에 풀업 트랜지스터 P1 및 풀다운 트랜지스터 N1이 직렬 접속되고, 풀업 트랜지스터 P1의 게이트단자에는 제1 및 제2 입력신호를 입력으로 하는 상기 크로스커플 래치회로의 출력신호가 공급되고, 풀다운 트랜지스터 N1의 게이트단자에는 상기 제1 및 제2입력신호를 입력으로 하는 상기 크로스커플 래치회로의 또다른 출력신호가 지연회로를 포함하는 2단계 출력 구동회로를 통해 공급되도록 구성되는 것을 특징으로 하는 반도체 소자의 출력버퍼회로.The pull-up transistor P1 and the pull-down transistor N1 are connected in series between the power supply and the ground, and the output signal of the cross-coupled latch circuit for inputting the first and second input signals is supplied to the gate terminal of the pull-up transistor P1, and the pull-down transistor N1 The gate terminal is configured to supply another output signal of the cross-coupled latch circuit for inputting the first and second input signals through a two-stage output driving circuit including a delay circuit. Buffer circuit. 제1항에 있어서, 상기 크로스커플 래치회로는 제1입력신호 및 반전게이트를 경유한 제2입력신호를 각각 입력으로 하는 낸드게이트와, 상기 제1입력신호 및 제 2입력신호를 각각 입력으로 하는 노아게이트와, 상기 낸드게이트의 출력을 어느 한 입력으로 하는 노아게이트와, 상기 노아게이트의 출력을 어느 한 입력으로 하는 낸드게이트와, 상기 노아게이트의 출력을 입력으로 하는 반전게이트와, 상기 낸드게이트의 출력을 입력으로 하는 반전게이트와, 상기 반전게이트의 출력이 상기 낸드게이트의 다른 한 입력단자로 접속되며, 상기 반전게이트의 출력은 상기 노아게이트의 다른 한 입력단자로 접속 구성되는 것을 특징으로 하는 반도체 소자의 출력버퍼 회로.2. The cross-coupled latch circuit according to claim 1, wherein the cross-coupled latch circuit is configured to input a NAND gate as the input of the first input signal and the second input signal via the inverted gate, and the first input signal and the second input signal, respectively. A noah gate, a noah gate having the output of the NAND gate as one input, a NAND gate having the output of the noah gate as either input, an inverting gate having the output of the noah gate as an input, and the NAND gate An inverted gate having an output of?, And an output of the inverted gate connected to the other input terminal of the NAND gate, and an output of the inverted gate connected to the other input terminal of the noah gate Output buffer circuit of semiconductor device. 제1항에 있어서, 상기 2단계 출력회로는 전원 및 접지간에 전류미러 및 패스 트랜지스터가 직렬로 접속되고, 상기 패스 트랜지스터의 게이트단자에는 상기 크로스커플 래치회로의 낸드게이트의 출력신호가 공급되고, 상기 전류미러의 NMOS트랜지스터의 게이트단자에는 상기 크로스커플 래치회로의 출력신호가 공급되고, 상기 전류미러의 PMOS트랜지스터의 게이트단자에는 상기 크로스커플 래치회로의 출력신호가 지연회로를 통해 공급되도록 구성되는 것을 특징으로 하는 반도체 소자의 출력버퍼 회로.The output circuit of the NAND gate of the cross-coupled latch circuit is supplied with a current mirror and a pass transistor connected in series between a power supply and a ground, and a gate terminal of the pass transistor. The output terminal of the cross-coupled latch circuit is supplied to the gate terminal of the NMOS transistor of the current mirror, and the output signal of the cross-coupled latch circuit is supplied to the gate terminal of the PMOS transistor of the current mirror through a delay circuit. An output buffer circuit for a semiconductor device. 제1항에 있어서, 상기 지연회로는 상기 크로스커플 래치회로의 출력신호 및 다수의 반전게이트를 통한 상기 크로스커플 래치회로의 출력신호를 각각 입력으로 하는 낸드게이트로 구성되는 것을 특징으로 하는 반도체 소자의 출력버퍼 회로.The semiconductor device of claim 1, wherein the delay circuit comprises a NAND gate configured to respectively input an output signal of the crosscouple latch circuit and an output signal of the crosscouple latch circuit through a plurality of inverted gates. Output buffer circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950022780A 1995-07-28 1995-07-28 Output buffer in semiconductor KR0139859B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950022780A KR0139859B1 (en) 1995-07-28 1995-07-28 Output buffer in semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950022780A KR0139859B1 (en) 1995-07-28 1995-07-28 Output buffer in semiconductor

Publications (2)

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KR970008891A true KR970008891A (en) 1997-02-24
KR0139859B1 KR0139859B1 (en) 1999-03-20

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980006065A (en) * 1996-06-27 1998-03-30 김주용 Method for forming a junction region of a semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100575610B1 (en) * 1999-08-18 2006-05-03 매그나칩 반도체 유한회사 Port circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980006065A (en) * 1996-06-27 1998-03-30 김주용 Method for forming a junction region of a semiconductor device

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