KR970008623A - Semiconductor Memory Device Manufacturing Method - Google Patents

Semiconductor Memory Device Manufacturing Method Download PDF

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Publication number
KR970008623A
KR970008623A KR1019950020368A KR19950020368A KR970008623A KR 970008623 A KR970008623 A KR 970008623A KR 1019950020368 A KR1019950020368 A KR 1019950020368A KR 19950020368 A KR19950020368 A KR 19950020368A KR 970008623 A KR970008623 A KR 970008623A
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South Korea
Prior art keywords
forming
insulating film
pattern
side wall
conductive layer
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KR1019950020368A
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Korean (ko)
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KR0151268B1 (en
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박순덕
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문정환
Lg 반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)

Abstract

본 발명은 반도체 메모리장치 제조방법에 관한 것으로, 이중 측벽(double sidewall)을 이용한 트렌치에 의한 소자분리를이용하여 고집적화에 유리한 구조의 EPROM를 제조하기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and to fabricate an EPROM having a structure advantageous for high integration by using device isolation by trenches using double sidewalls.

본 발명은 반도체기판상에 패드층과 버퍼층을 차례로 형성하는 공정과, 상기 버퍼층을 선택적으로 식각하여 소자가 형성될 액치브영역을 정의하는 소정의 버퍼층패턴을 형성하는 공정, 상기 버퍼층패턴의 측면에 제1측벽을 형성하는 공정, 상기 버처층패턴 및 제1측벽을 마스크로 이용하여 상기 패드층을 식각하여 패드층패텬을 형성하는 공정, 상기 패드층패턴측면에 제2측벽을 형성하는 공정, 상기 버퍼층패턴과 제1측벽 및 제2측벽을 마스크로 이용하여 노출된 기판 부위를 식각하여 트렌치를 형성하는 공정, 상기 트렌치 내벽에 얇은 산화막을 형성하는 공정, 상기 트렌치내에 절연막을 매립하는 공정, 상기 버퍼층패턴, 제1측벽, 제2측벽 및 패드층패턴을 제거하는 공정, 기판 전면에 게이트산화막을 형성하는 공정, 상기 게이트산화막상에 제1도전층을 형성하는 공정, 상기 제1도전층을 액티브영역 패턴으로 패터닝하는 공정, 상기 제1도전층 전면에 층간절연막을 형성하는 골정, 상기 층간절연막 상부에 제2도전층을 형성하는 골정, 상기 제2도전층상에 절연막을 형성하는 공정, 상기 절연막과 제2도전층을 소정패턴으로 패터닝하여 게이트 캡절연막 및 게이트를 형성하는 공정, 및상기 게이트 캡절연막을 마스크로 이용하여 상기 층간절연막 및 제1도전층을 식각하여 플로팅 게이트를 형성하는 공정을포함하여 이루어지는 반도체 메모리장치 제조방법을 제공한다.The present invention provides a process of forming a pad layer and a buffer layer sequentially on a semiconductor substrate, forming a predetermined buffer layer pattern to selectively define an etched region where an element is to be formed by selectively etching the buffer layer, and at the side of the buffer layer pattern. Forming a first side wall, forming a pad layer pattern by etching the pad layer using the green layer pattern and the first side wall as a mask, forming a second side wall on the side of the pad layer pattern, and Forming a trench by etching the exposed substrate portion using the buffer layer pattern and the first side wall and the second side wall as a mask, forming a thin oxide film on the inner wall of the trench, embedding an insulating film in the trench, and the buffer layer Removing the pattern, the first side wall, the second side wall, and the pad layer pattern; forming a gate oxide film on the entire surface of the substrate; Forming a layer; forming a first conductive layer in an active region pattern; forming a interlayer insulating film on an entire surface of the first conductive layer; forming a second conductive layer on the interlayer insulating film; Forming an insulating film on the conductive layer, patterning the insulating film and the second conductive layer in a predetermined pattern to form a gate cap insulating film and a gate, and using the gate cap insulating film as a mask, the interlayer insulating film and the first conductive layer It provides a method of manufacturing a semiconductor memory device comprising the step of forming a floating gate by etching.

Description

반도체 메모리장치 제조방법Semiconductor Memory Device Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 EPROM 제조방법을 도시한 공정순서도.2 is a process flowchart showing the EPROM manufacturing method according to the present invention.

Claims (6)

반도체기판상에 패드층과 버퍼층을 차례로 형성하는 공정과, 상기 버퍼층을 선택적으로 식각하여 소자가형성될 액티브영역을 정의하는 소정의 버퍼층패턴을 형성하는 공정, 상기 버퍼층패턴의 측면에 제1측벽을 형성하는 공정,상기 버퍼층패턴 및 제1측벽을 바스크로 이용하여 상기 패드층을 식각하여 패드층패턴을 형성하는 공정, 상기 패드층패턴측면에 제2측벽을 형성하는 공정, 상기 버퍼층패턴과 제1측벽 및 제2측벽을 마스크로 이용하여 노출된 기판 부위를 식각하여 트렌치를 형성하는 공정, 상기 트렌치 내벽에 얇은 산화막을 형성하는 공정, 상기 트렌치내에 절연막을 매립하는 공정, 상기 버퍼층패턴, 제1측벽, 제2측벽 및 패드층패턴을 제거하는 공정, 기판 전면에 게이트산화막을 형성하는 공정, 상기 게이트산화막상에 제1도전층을 형성하는 공정, 상기 제1도전층을 액티브영역 패턴으로 패터닝하는 공정, 상기 제1도전층 전면에 층간절연막을 형성하는 공정, 상기 층간절연막 상부에 제2도전층을 형성하는 공정, 상기 제2도전층상에 절연막을 형성하는 공정, 상기 절연막과 제2도전층을 소정패턴으로 패터닝하여 게이트 캡절연막 및 게이트를 형성하는 공정, 및상기 게이트 캡절연막을 마스크로 이용하여 상기 층간절연막 및 제1도전층을 식각하여 플로팅 게이트를 형성하는 공정을포함하여 이루어지는 것을 특징으로 하는 반도체 메모리장치 제조방법.Forming a pad layer and a buffer layer sequentially on the semiconductor substrate, and selectively etching the buffer layer to form a predetermined buffer layer pattern defining an active region in which the device is to be formed, and forming a first side wall on the side of the buffer layer pattern. Forming a pad layer pattern by etching the pad layer using the buffer layer pattern and the first side wall as a basque, forming a second side wall on the side surface of the pad layer pattern, the buffer layer pattern and the first side wall Forming a trench by etching exposed substrate portions using sidewalls and second sidewalls as a mask, forming a thin oxide film on the inner wall of the trench, embedding an insulating film in the trench, the buffer layer pattern, and the first sidewall Removing the second side wall and the pad layer pattern, forming a gate oxide film on the entire surface of the substrate, and forming a first conductive layer on the gate oxide film. Process, patterning the first conductive layer into an active region pattern, forming an interlayer insulating film over the first conductive layer, forming a second conductive layer over the interlayer insulating film, and forming a second conductive layer on the second conductive layer. Forming an insulating film, patterning the insulating film and the second conductive layer in a predetermined pattern to form a gate cap insulating film and a gate, and etching the interlayer insulating film and the first conductive layer using the gate cap insulating film as a mask. A method of manufacturing a semiconductor memory device, comprising the step of forming a floating gate. 제1항에 있어서, 상기 제1도전층을 액티브영역 패턴으로 패터닝하는 공정후에 기판 전면에 절연막을 증착한 후 에치백하여 인접한 액티브영역상의 각각의 제1도전층간을 절연시키는 공정이 더 포함되는 것을 특징으로 하는 반도체 메모리장치 제조방법.The method of claim 1, further comprising, after the step of patterning the first conductive layer into an active region pattern, depositing an insulating film on the entire surface of the substrate and then etching back to insulate each of the first conductive layers on the adjacent active region. A semiconductor memory device manufacturing method characterized by the above-mentioned. 제1항에 있어서, 상기 패드층은 산화막으로 형성하는 것을 특징으로 하는 반도체 메모리장치 제조방법.The method of claim 1, wherein the pad layer is formed of an oxide film. 제1항에 있어서, 상기 버퍼층은 질화막으로 형성하는 것을 특징으로 하는 반도체 메모리장치 제조방법.The method of claim 1, wherein the buffer layer is formed of a nitride film. 제1항에 있어서, 상기 제1측벽은 상기 버퍼층패턴을 형성한 후, 기판 전면에 LTO를 증착하고 이를 에치백하여 형성하는 것을 특징으로 하는 반도체 메모리장치 제조방법.The method of claim 1, wherein the first side wall is formed by depositing LTO on the entire surface of the substrate and etching back the buffer layer pattern. 제1항에 있어서, 상기 제2측벽은 상기 패드층패턴을 형성한 후, 기판 전면에 HTO를 증착하고 이를 에치백하여 형성하는 것을 특징으로 하는 반도체 메모리장치 제조방법.The method of claim 1, wherein the second side wall is formed by depositing HTO on the entire surface of the substrate and etching back the pad layer pattern. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950020368A 1995-07-11 1995-07-11 Method of manufacturing semiconductor memory device KR0151268B1 (en)

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KR1019950020368A KR0151268B1 (en) 1995-07-11 1995-07-11 Method of manufacturing semiconductor memory device

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KR0151268B1 KR0151268B1 (en) 1998-10-01

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KR100452313B1 (en) * 1997-07-04 2005-05-03 삼성전자주식회사 Nonvolatile Memory Device and Manufacturing Method

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