KR970008340B1 - Method for manufacturing a semiconductor device - Google Patents

Abstract

A method of fabricating a semiconductor device includes the steps of forming a field region in a semiconductor substrate for defining an active region, ion-implanting a first conductivity type first dopant into the overall surface of the semiconductor substrate in which the field region is formed, to form a first impurity region having the first conductivity, ion-implanting a first conductivity type second dopant into a first region of the semiconductor substrate, in which the first impurity region is formed, to form a first conductivity type first well, and ion-implanting a second conductivity type third dopant into a second region of the semiconductor substrate, in which the first well is formed, to form a second conductivity type second well.

Description

Manufacturing Method of Semiconductor Device

1 is a graph simulating impurity distribution of conventional diffusion wells and retrolled wells.

2 is a cross-sectional view simulating an NMOS transistor to which a conventional retrograde P well is applied.

3 and 4 are graphs simulating impurity distributions in the active region and the isolation region, respectively, for a conventional retrograde P well.

5 to 8 are cross-sectional views illustrating a method for manufacturing a retrolog well according to the present invention.

9 is a cross-sectional view simulating an NMOS transistor to which a retrolled P well according to the first embodiment of the present invention is applied.

10 and 11 are graphs simulating impurity distribution states in the active region and the isolation region of the retrograde P well according to the first embodiment of the present invention.

12 is a cross-sectional view simulating an NMOS transistor to which a reloglaed P well according to a second embodiment of the present invention is applied.

13 and 14 are graphs simulating impurity distribution states in the active region and the isolation region of the retrograde P well according to the second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

C: Channel ion implantation F: Field ion implantation

W: Well ion implantation CD: Counter-doped ion implantation

10 semiconductor substrate 12 field oxide film

14: sacrificial oxide film 18: counter doping region

20: insulating film 26, 30: retrolled N well and P well

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of reducing the substrate bias voltage dependence of a threshold voltage in a MOS transistor to which a retrograde well is applied. .

In conventional CMOS (Complementary MOS) technology, a well is formed by implanting a dopant and then diffusing it to an appropriate depth (hereinafter referred to as "diffusion well"). However, according to the above method, since diffusion also proceeds in the lateral direction, a problem arises in that the degree of integration decreases.

Therefore, a method of forming a well by high energy ion implantation has been developed so that the dopant is located at an appropriate depth without a diffusion process, and the well shows a peak value of impurity concentration at a certain depth in the silicon substrate and reaches the substrate surface. It is called a retrolog well because the impurity concentration gradually decreases. The retrolled well is a high contribution to the process cost reduction by eliminating the high temperature, long time diffusion process used in the conventional diffusion well, suppresses latch-up (soft error rate), etc. Has the advantage of improving the electrical properties.

1 is a graph simulating impurity distribution of a conventional diffusion well and a retrolog well.

Referring to FIG. 1, the conventional retrolled well, for example, in the case of a P well, performs a well ion implantation (W) with boron at an energy of about 700 to 800 keV, and then enters a field with an energy of about 130 to 300 keV. The retranslated N well is formed by performing ion implantation (F). Further, in order to improve the punch-through characteristics of the NMOS transistor, a high concentration of ion implantation is performed.

In the conventional retrodewell process described above, well ion implantation (W) serves to suppress latchup and soft errors, and field ion implantation (F) determines device isolation characteristics. In addition, the field ion implantation (F) also affects the active region where the transistor is formed, resulting in a change in the electrical characteristics of the transistor. Therefore, as shown in FIG. 1, when the dose and energy of the field ion implantation (F) are determined to enhance the device isolation characteristics, the surface concentration of the active region is increased as compared with the conventional diffusion well. The change in the threshold voltage due to the bias voltage between the source and the substrate (hereinafter referred to as the "body effect") is increased.

In particular, in the case of NMOS transistors using retrolled wells, the body effect is further increased, which is a major cause of speed reduction during operation of the device. A cross-sectional view of a simulation of an NMOS transistor to which a conventional retranslated P well is applied is shown in FIG. 2, and FIGS. 3 and 4 are graphs simulating impurity distribution in an active region and an isolation region. The depletion layer shown in FIG. 2 was calculated under a gate voltage of 1.5V, a drain voltage of 0.1V, and a substrate voltage of -1.0V, and the maximum depletion depth (reference numeral X in FIG. 3) became 0.21 mu m.

In the conventional CMOS technology, since the circuit is mainly composed of NMOS transistors, it is important to reduce the body effect of the NMOS transistors in order to prevent the operation speed of the device from decreasing.

Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device capable of reducing the body effect of a MOS transistor to which a retrolog well is applied.

In order to achieve the above object, the present invention comprises the steps of forming a separation region for defining an active region on a semiconductor substrate; Forming a first impurity region of a first conductive type by ion implanting a first conductive type of a first conductive type onto an entire surface of the semiconductor substrate on which the separation region is formed; Forming a first well of a first conductive type by ion implanting a second conductive type of a first conductive type into a first region of the semiconductor substrate on which the first impurity is formed; And ion implanting a third conductive dopant of a second conductivity type into a second region of the semiconductor substrate on which the first well is formed to form a second well of a second conductive type. Provide a method.

The forming of the first impurity region of the first conductive type is preferably performed when the thickness of the separation region is maximized in order to minimize the influence of the first impurity region on the separation region.

Further, in the forming of the first well, after the ion implantation of the second conductive dopant of the first conductivity type, the ion implantation of the first conductive type dopant may be further provided one or more times. The same applies to the two wells.

According to a preferred embodiment of the present invention, an N-type first dopant of a conductivity type opposite to a retrolled P well in which an NMOS transistor is formed is ion-implanted on the entire surface of the semiconductor substrate to form an N-type counter-doping region. As a result, the body effect of the NMOS transistor is reduced by compensating the surface concentration of the retrode P well to the concentration of the N-type first dopant.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 to 8 are cross-sectional views illustrating a method for manufacturing a retrolog well according to the present invention.

5 shows a step of forming the field oxide film 12. As shown in FIG. In order to distinguish the active region and the device isolation region on the P-type (or N-type) semiconductor substrate 10, a field oxide film 12 having a thickness of 4,500 Å is formed by applying a conventional SEPOX method. . Subsequently, in order to remove the white ribbon, which may occur when the field oxide layer 12 is formed, a surface oxide of the substrate 10 is thinly oxidized by a thermal oxidation process, and a sacrificial oxide layer having a thickness of 500 μm is used. 14). Here, the thickness of the field oxide film 12 after the sacrificial oxide film 14 is formed is about 4,700 kPa.

6 shows the step of forming an N-type counter doped region 18. N-type first dopant 16, for example, an ion implanted at 1.0E12 / cm 2 dose and energy of 160 to 200 keV on the entire surface of the substrate 10 on which the sacrificial oxide film 14 is formed, thereby counter-doping N-type. Area 18 is formed. According to a preferred embodiment of the present invention, the counter doped region 18 is formed. According to a preferred embodiment of the present invention, in order to prevent the counter-doped region 18 from penetrating below the field oxide film, the ion oxide film 12 is formed to maximize the thickness of the field oxide film 12 by forming the sacrificial oxide film 14. Carry out an injection.

FIG. 7 illustrates the step of forming the relogla N well 26. The photoresist is applied to the entire surface of the substrate 10 on which the N-type counter doped region 18 is formed, and then the photoresist is exposed and developed by applying a mask (not shown) to form an N well. The first photoresist pattern 22 is formed in the region of the substrate 10 except for the region where the N well is to be formed. Subsequently, using the first photoresist pattern 22 as a mask, an N-type second dopant 24 such as phosphorus is ion-implanted one or more times by appropriately adjusting the dose and energy, thereby retreating the N well 26. ). Here, the first photoresist pattern 22 is formed to have a thickness sufficient to prevent penetration into the P well region to be formed later, when high energy ion implantation is performed to form the retrolled N well 26. It is preferable.

8 shows the step of forming the reloglaed P well 30. After removing the first photoresist pattern of FIG. 7, the photoresist is applied to the entire surface of the substrate 10, and the photoresist is exposed and developed by applying a mask (not shown) to form a P well. The second photoresist pattern 27 is formed only on the substrate on which the N well 26 is formed. In this case, the second photoresist pattern 27 is preferably formed to a thickness sufficient to prevent the penetration into the retrolled N well during the high energy ion implantation to form the retrolled P well. Subsequently, using the second photoresist pattern 27 as a mask, ion-implanted a P-type third dopant 28 such as boron under a first condition of 700 keV and 1.0E13 / cm 2, followed by 130 keV and 5.0 Ion implantation is carried out under a second condition of E12 / cm 2 to form the retrode P well 30. Here, the ion implantation of the first condition is performed to control the peak concentration of the well, and the ion implantation of the second condition is performed to serve as a channel stopper in the separation region. After performing the ion implantation under the first and second conditions, in order to adjust the threshold voltage of the NMOS transistor, for example, boron fluoride is ion implanted under a condition of 40 keV and 1.0E12 / cm 2, and the second photoresist pattern 27 ). Subsequent processes proceed in the same manner as in conventional CMOS processes.

According to the above-described manufacturing method of the present invention, an ion implantation of an N-type first dopant of a conductivity type opposite to that of a retrolled P well in which an NMOS transistor is to be formed on the entire surface of the semiconductor substrate is performed to lower the surface concentration of the retrolled P well. As a result, the body effect of the NMOS transistor can be reduced. In addition, since the ion implantation is performed on the entire surface of the substrate, punch-through characteristics can be improved by increasing the N well concentration near the source and drain regions in the case of PMOS transistors.

In addition, since the N-type first dopant is ion implanted after the formation of the sacrificial oxide film in which the thickness of the field oxide film is maximized, the N-type first dopant is as deep as possible in the active region in the retrograde P well. On the other hand, the N-type first dopant cannot penetrate under the field oxide layer. Here, of course, the ion implantation of the N-type first dopant is not necessarily performed after the sacrificial oxide film is formed.

FIG. 9 is a cross-sectional view of a first embodiment of the present invention, that is, an NMOS transistor in which the N-type counter doping region (reference numeral 18 in FIG. 6) is formed under the condition of 1.0E12 / cm 2 and 160 keV. 10 and 11 are graphs simulating impurity distribution states in the active region and the isolation region, respectively, according to the first embodiment.

9 to 11, a voltage of 1.5 V is applied to the gate of the NMOS transistor, -1.0 V is applied to the substrate, 0.1 V is applied to the drain, and the source is grounded. The depletion layer of the NMOS transistor was calculated.

According to the depletion approximation model, the depletion depth X _d is

X _d = [2 μ (2ψ _B + V _SB ) / (qN _A )] ^1/2 . … … … … … … … … … … … … … (One)

And the maximum depletion depth X is

X = [(4∈ψ _B ) / (qN _A )] ^1/2 . … … … … … … … … … … … … … … … … (2)

Becomes Where ∈ is the silicon dielectric constant, ψ _B is the Fermi potential, V _SB is the voltage between the source and the substrate, and N _A is the concentration of the acceptor.

Therefore, the threshold voltage Vth is

Vth = V _FB + 2ψ _B + γ (2ψ _B + V _SB ) ^1/2 ... … … … … … … … … … … … … … … … … (3)

Where γ is

γ = (2∈qN _A ) ^1/2 / Cox. … … … … … … … … … … … … … … … … … … … … (4)

The body effect is determined as a "substrate effect constant" defined by.

As can be seen from Equation (4), the substrate effect constant γ that influences the body effect is proportional to the acceptor concentration, for example, 1/2 power of the concentration N _A of boron. Also, as can be seen from equation (2), the maximum depletion depth X is inversely proportional to the 1/2 power of N _A. Therefore, the maximum depth of depletion is 0.21 μm for the conventional retrode P well shown in FIG. 3, and the maximum depth of depletion X is 0.26 μm for the first embodiment of the present invention shown in FIG. 10. It can be seen that the body effect of the NMOS transistor to which the inventive retrolled P well is applied is reduced.

In other words, as shown in FIG. 10, in the first embodiment of the present invention, N-type phosphorus is ion implanted (reference CD) under the condition of 1.0E12 / cm 2 and 160 keV, namely, the surface of the retrode P well. In the region where the channel of the NMOS transistor is formed (reference C), the boron concentration is canceled to the phosphorus concentration. Thus, the net concentration at the P well surface is significantly reduced than the conventional P well shown in FIG. 3, resulting in a lower body effect than conventional.

Phosphorus implanted under the condition of 1.0E12 / cm 2 and 160keV does not penetrate the field oxide film as shown in FIG. 11 and thus does not affect device isolation characteristics.

FIG. 12 is a cross-sectional view of a second embodiment of the present invention, that is, an NMOS transistor in which the N-type counter doping region (reference numeral 18 in FIG. 6) is formed under the condition of 1.0E12 / cm 2 and 200 keV. 13 and 14 are graphs simulating impurity distribution states in the active region and the isolation region, respectively, according to the second embodiment.

12 to 14, it can be seen that as in the first embodiment of the present invention described above, the maximum depletion depth X is 0.26 μm, which reduces the body effect of the NMOS transistor. Further, as shown in FIG. 14, ion implantation (reference CD) of phosphorus at an energy of 200 keV penetrates to the bottom of the field oxide film, but the effect on device isolation characteristics is very small because of its low concentration.

As described above, according to the present invention, the first conductive type MOS transistor mainly determining the CMOS operating speed is formed, and the first conductive type first conductive MOS transistor is opposite to the dopant forming the first well of the second conductive type. Ion implantation of the dopant over the entire surface of the semiconductor substrate lowers the surface concentration of the first well. As a result, speed reduction can be prevented by reducing the body effect of the first conductive MOS transistor.

In addition, since the first dopant of the first conductivity type is ion implanted at the maximum thickness of the isolation region, not only does it affect the device isolation characteristics, but also the first implant is performed on the entire surface of the substrate. The concentration of the second well of the conductive type may be locally increased to improve punchthrough characteristics of the second conductive MOS transistor to be formed in the second well.

Claims (4)

Forming an isolation region for defining an active region on the semiconductor substrate; Forming a first impurity region of the first conductive type by ion implantation of a first conductive type of the first conductive type on the entire surface of the semiconductor substrate on which the separation region is formed; Forming a first well of a first conductive type by ion implanting a second conductive type of a first conductive type into a first region of the semiconductor substrate on which the first impurity region is formed; And ion-implanting a second conductive type third dopant into a second region of the semiconductor substrate on which the first well is formed to form a second well of a second conductive type. Manufacturing method. The method of claim 1, wherein in the forming of the first well of the first conductive type, after ion implanting the second conductive type of the first conductive type, ion implanting the dopant of the first conductive type is performed. A method of manufacturing a semiconductor device, characterized in that it further comprises one or more times. The method of claim 1, wherein in the forming of the second well of the second conductive type, after ion implanting the third conductive type of the second conductive type, ion implanting the dopant of the second conductive type is performed. A method of manufacturing a semiconductor device, characterized in that it further comprises one or more times. The method of claim 1, wherein the forming of the first impurity region of the first conductivity type is performed when the thickness of the isolation region is maximized.