KR970008194B1 - Method and apparatus for providing back-to-back data transfers in an information handling system having a multiplexed bus - Google Patents
Method and apparatus for providing back-to-back data transfers in an information handling system having a multiplexed bus Download PDFInfo
- Publication number
- KR970008194B1 KR970008194B1 KR94011539A KR19940011539A KR970008194B1 KR 970008194 B1 KR970008194 B1 KR 970008194B1 KR 94011539 A KR94011539 A KR 94011539A KR 19940011539 A KR19940011539 A KR 19940011539A KR 970008194 B1 KR970008194 B1 KR 970008194B1
- Authority
- KR
- South Korea
- Prior art keywords
- handling system
- information handling
- data transfers
- multiplexed bus
- providing
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/068,882 US5448703A (en) | 1993-05-28 | 1993-05-28 | Method and apparatus for providing back-to-back data transfers in an information handling system having a multiplexed bus |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970008194B1 true KR970008194B1 (en) | 1997-05-21 |
Family
ID=22085317
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR94011539A KR970008194B1 (en) | 1993-05-28 | 1994-05-26 | Method and apparatus for providing back-to-back data transfers in an information handling system having a multiplexed bus |
Country Status (6)
Country | Link |
---|---|
US (1) | US5448703A (ko) |
EP (1) | EP0627689A3 (ko) |
JP (1) | JP2571673B2 (ko) |
KR (1) | KR970008194B1 (ko) |
BR (1) | BR9402107A (ko) |
CA (1) | CA2124614A1 (ko) |
Families Citing this family (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5581793A (en) * | 1993-08-24 | 1996-12-03 | Micron Electronics, Inc. | System for bypassing setup states in a bus operation |
US5805834A (en) * | 1994-03-30 | 1998-09-08 | Zilog, Inc. | Hot reconfigurable parallel bus bridging circuit |
US5596765A (en) * | 1994-10-19 | 1997-01-21 | Advanced Micro Devices, Inc. | Integrated processor including a device for multiplexing external pin signals |
US5564114A (en) * | 1995-01-09 | 1996-10-08 | Cirrus Logic Inc. | Method and an arrangement for handshaking on a bus to transfer information between devices in a computer system |
US5608884A (en) * | 1995-05-17 | 1997-03-04 | Dell Usa, L.P. | Commonly housed multiple processor type computing system and method of manufacturing the same |
US5758171A (en) * | 1995-07-05 | 1998-05-26 | Cirrus Logic, Inc. | Apparatus and method for reading back socket power status information |
US5872992A (en) * | 1995-08-24 | 1999-02-16 | Motorola, Inc. | System and method for avoiding bus contention on a multiplexed bus by providing a time period subsequent to a read operation |
US5790814A (en) * | 1996-01-23 | 1998-08-04 | Dell U.S.A., L.P. | Technique for supporting semi-compliant PCI devices behind a PCI-to-PCI bridge |
US5873119A (en) * | 1996-02-09 | 1999-02-16 | Intel Corporation | Method for parallel processing of dram read request in a memory-cache controller system |
US5678009A (en) * | 1996-02-12 | 1997-10-14 | Intel Corporation | Method and apparatus providing fast access to a shared resource on a computer bus |
US5924128A (en) * | 1996-06-20 | 1999-07-13 | International Business Machines Corporation | Pseudo zero cycle address generator and fast memory access |
US5784580A (en) * | 1996-06-28 | 1998-07-21 | International Business Machines Corporation | System and method for communicating between devices |
US5857080A (en) * | 1996-09-10 | 1999-01-05 | Lsi Logic Corporation | Apparatus and method for address translation in bus bridge devices |
US5867645A (en) * | 1996-09-30 | 1999-02-02 | Compaq Computer Corp. | Extended-bus functionality in conjunction with non-extended-bus functionality in the same bus system |
KR100224965B1 (ko) * | 1997-07-10 | 1999-10-15 | 윤종용 | 다층 구조의 아이2씨 버스를 이용한 진단/제어 시스템 |
US6018784A (en) * | 1997-07-31 | 2000-01-25 | Trimble Navigation Limited | PCI card for receiving a GPS signal |
US6151654A (en) * | 1997-12-24 | 2000-11-21 | Intel Corporation | Method and apparatus for encoded DMA acknowledges |
US7395302B2 (en) | 1998-03-31 | 2008-07-01 | Intel Corporation | Method and apparatus for performing horizontal addition and subtraction |
US6418529B1 (en) | 1998-03-31 | 2002-07-09 | Intel Corporation | Apparatus and method for performing intra-add operation |
US7392275B2 (en) * | 1998-03-31 | 2008-06-24 | Intel Corporation | Method and apparatus for performing efficient transformations with horizontal addition and subtraction |
US6961801B1 (en) | 1998-04-03 | 2005-11-01 | Avid Technology, Inc. | Method and apparatus for accessing video data in memory across flow-controlled interconnects |
US6266731B1 (en) * | 1998-09-03 | 2001-07-24 | Compaq Computer Corporation | High speed peripheral interconnect apparatus, method and system |
US6816934B2 (en) * | 2000-12-22 | 2004-11-09 | Hewlett-Packard Development Company, L.P. | Computer system with registered peripheral component interconnect device for processing extended commands and attributes according to a registered peripheral component interconnect protocol |
US6178478B1 (en) * | 1998-12-11 | 2001-01-23 | Vlsi Technology, Inc. | Smart target mechanism for eliminating dual address cycles in a peripheral component interconnect environment |
GB2362482A (en) | 2000-05-15 | 2001-11-21 | Ridgeway Systems & Software Lt | Direct slave addressing to indirect slave addressing |
US6950893B2 (en) * | 2001-03-22 | 2005-09-27 | I-Bus Corporation | Hybrid switching architecture |
US6823441B1 (en) | 2001-04-20 | 2004-11-23 | Daimlerchrysler Corporation | Method of multiplexed address and data bus |
US7020788B2 (en) | 2001-06-01 | 2006-03-28 | Microchip Technology Incorporated | Reduced power option |
US6728856B2 (en) | 2001-06-01 | 2004-04-27 | Microchip Technology Incorporated | Modified Harvard architecture processor having program memory space mapped to data memory space |
US6601160B2 (en) | 2001-06-01 | 2003-07-29 | Microchip Technology Incorporated | Dynamically reconfigurable data space |
US6552625B2 (en) | 2001-06-01 | 2003-04-22 | Microchip Technology Inc. | Processor with pulse width modulation generator with fault input prioritization |
US6937084B2 (en) | 2001-06-01 | 2005-08-30 | Microchip Technology Incorporated | Processor with dual-deadtime pulse width modulation generator |
US6975679B2 (en) | 2001-06-01 | 2005-12-13 | Microchip Technology Incorporated | Configuration fuses for setting PWM options |
US6934728B2 (en) | 2001-06-01 | 2005-08-23 | Microchip Technology Incorporated | Euclidean distance instructions |
US20020184566A1 (en) | 2001-06-01 | 2002-12-05 | Michael Catherwood | Register pointer trap |
US6976158B2 (en) | 2001-06-01 | 2005-12-13 | Microchip Technology Incorporated | Repeat instruction with interrupt |
US7003543B2 (en) | 2001-06-01 | 2006-02-21 | Microchip Technology Incorporated | Sticky z bit |
US7007172B2 (en) | 2001-06-01 | 2006-02-28 | Microchip Technology Incorporated | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection |
US6985986B2 (en) | 2001-06-01 | 2006-01-10 | Microchip Technology Incorporated | Variable cycle interrupt disabling |
US6604169B2 (en) | 2001-06-01 | 2003-08-05 | Microchip Technology Incorporated | Modulo addressing based on absolute offset |
US7467178B2 (en) | 2001-06-01 | 2008-12-16 | Microchip Technology Incorporated | Dual mode arithmetic saturation processing |
US6952711B2 (en) | 2001-06-01 | 2005-10-04 | Microchip Technology Incorporated | Maximally negative signed fractional number multiplication |
US6907503B2 (en) * | 2001-09-27 | 2005-06-14 | Daimlerchrysler Corporation | Dual port RAM communication protocol |
US20040021483A1 (en) * | 2001-09-28 | 2004-02-05 | Brian Boles | Functional pathway configuration at a system/IC interface |
US6552567B1 (en) | 2001-09-28 | 2003-04-22 | Microchip Technology Incorporated | Functional pathway configuration at a system/IC interface |
US20040059862A1 (en) * | 2002-09-24 | 2004-03-25 | I-Bus Corporation | Method and apparatus for providing redundant bus control |
JP2004334410A (ja) | 2003-05-06 | 2004-11-25 | Hitachi Ltd | 情報処理装置及びプロセッサ |
US7536615B1 (en) | 2007-03-26 | 2009-05-19 | Lattice Semiconductor Corporation | Logic analyzer systems and methods for programmable logic devices |
US7743296B1 (en) | 2007-03-26 | 2010-06-22 | Lattice Semiconductor Corporation | Logic analyzer systems and methods for programmable logic devices |
KR20100078193A (ko) * | 2008-12-30 | 2010-07-08 | 주식회사 동부하이텍 | 슬레이브 및 그와 마스터 간의 통신 방법 |
JP5600517B2 (ja) * | 2010-08-18 | 2014-10-01 | キヤノン株式会社 | 情報処理装置、情報処理方法、およびプログラム |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4112490A (en) * | 1976-11-24 | 1978-09-05 | Intel Corporation | Data transfer control apparatus and method |
US4463421A (en) * | 1980-11-24 | 1984-07-31 | Texas Instruments Incorporated | Serial/parallel input/output bus for microprocessor system |
US4752763A (en) * | 1986-07-11 | 1988-06-21 | Mai Basic Four, Inc. | Binary comparison circuit with selectable binary digit override |
US4878166A (en) * | 1987-12-15 | 1989-10-31 | Advanced Micro Devices, Inc. | Direct memory access apparatus and methods for transferring data between buses having different performance characteristics |
JPH01239627A (ja) * | 1988-03-18 | 1989-09-25 | Nec Corp | 一致検出回路 |
US5191656A (en) * | 1991-08-29 | 1993-03-02 | Digital Equipment Corporation | Method and apparatus for shared use of a multiplexed address/data signal bus by multiple bus masters |
CA2080210C (en) * | 1992-01-02 | 1998-10-27 | Nader Amini | Bidirectional data storage facility for bus interface unit |
-
1993
- 1993-05-28 US US08/068,882 patent/US5448703A/en not_active Expired - Fee Related
-
1994
- 1994-05-24 JP JP6109394A patent/JP2571673B2/ja not_active Expired - Lifetime
- 1994-05-25 EP EP94303785A patent/EP0627689A3/en not_active Withdrawn
- 1994-05-26 KR KR94011539A patent/KR970008194B1/ko not_active IP Right Cessation
- 1994-05-27 BR BR9402107A patent/BR9402107A/pt not_active Application Discontinuation
- 1994-05-30 CA CA002124614A patent/CA2124614A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
BR9402107A (pt) | 1994-12-13 |
CA2124614A1 (en) | 1994-11-29 |
EP0627689A3 (en) | 1996-07-17 |
US5448703A (en) | 1995-09-05 |
JPH0713908A (ja) | 1995-01-17 |
EP0627689A2 (en) | 1994-12-07 |
JP2571673B2 (ja) | 1997-01-16 |
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Legal Events
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A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20010714 Year of fee payment: 5 |
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