KR970005618B1 - Multi-axis control circuit of robot - Google Patents

Abstract

Through the output terminal of the bus transceiver(Q4), an interrupt signal is generated. The interrupt signal is inputted to the programmable peripheral interface circuit and at the same time inputted to the inverter(N1) and is inverse. When an inversion signal is fed to the interrupt terminal of the microprocessor, the microprocessor performs the interrupt routine. the programmable peripheral interface circuit which receives an output interrupt signal of the bus transceiver, generates a data transmission control signal. Consequently the command data outputted from the programmable peripheral interface circuit is inputted to the microprocessor.

Description

Multi-axis control circuit for robot

1 is a conventional multi-axis control schematic.

2 is a block diagram according to the present invention.

3 is a detailed circuit diagram according to the present invention.

4 is an operational waveform diagram according to the present invention.

The present invention relates to a multi-axis control method in a robot, and more particularly, to a multi-axis control circuit for controlling loads of main controllers while simultaneously controlling a multi-axis robot having multiple joints.

In the conventional robot, in order to control the multi-axis according to the control, the AC servo motor 12a, 12b, 13c, 12d for each axis control is connected with a mechanical mechanism as shown in FIG. 1, and the AC servo motor 12a-12d is a motor controller. Controlled by 11a-11d. That is, when control data is input to the motor controllers 11a-11d according to a program processed by the main controller 10, the control data of the AC servomotor 12a-12d is controlled according to the value output from the motor controllers 11a-11d. The multi-axis motor for driving the articulated joint was to be controlled.

However, the load is increased because all the functions are collectively performed by the control processing of the program performed by the main controller 10, and the batch processing of the main controller 10 is performed by the sequential processing, so that the predetermined AC servomotor (12a) There was a problem that the processing for the control of the other AC servomotors 12b-13d was impossible during the control, and the program processing of the other functions of the main controller 10 was impossible.

Accordingly, an object of the present invention is to provide a circuit that can provide precise timing signals, which enables precise control, and that it is easy to insert other application functions in the main controller by distributing various functions of the main controller to the intermediate controller.

Another object of the present invention is to provide a circuit that can control other functions, easy A / S and simultaneously control the position of each axis regardless of program execution of main controller by using interrupt signal between controllers. .

The present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram according to the present invention, a main controller 10 for generating a control data by executing a program according to the multi-axis control of the robot, an AC servomotor 12a-12d for controlling each axis of the joint, After the interrupt routine is executed by the interrupt signal generated by the main controller 10, the command of the main controller 10 is interpreted to generate control data according to the analysis command, and the control data is converted into an analog signal. And an intermediate controller 13a-13d for transmitting to 11a-11d).

)에 프로그램어블 인터럽트 콘트롤러(PIC)가 연결되고 상기 프로그램어블 인터럽트 콘트롤러(PIC)로 부터 프로그램어블 인터벌타이머(PIT)를 연결하며, 상기 중앙처리장치(CPU)의 입출력 라이트단(I/OW)과 중앙처리장치(CPU)의 데이타버스(D0-D2)를 디코더(DE1)의 입력단에 연결하고, 상기 디코더(DEC1)의 출력단(S1-S4)이 JK플립플롭(JF1-JF4)의 클럭단(CK)에 연결되며, 상기 JK플립플롭(JF1-JF4)의 출력단(Q)이 버스트랜시버(BT)의 입력단(D1-D4)에 연결되고, 상기 버퍼트랜시버(BT)의 출력단(Q1-Q4)을 프로그램어블 패리페럴 인터페이스회로(PP1)를 연결하며, 상기 JK플립플롭(JF1-JF4)의 클리어단(CLR)이 버스드라이버(BD)의 출력단(Q1-Q4)을 접속한 구성이 주제어기(10)에 대응하고, 상기 버퍼트랜시버(BT)의 출력단(Q4)으로 부터 인버터(N1)를 연결하여 마이크로프로세서(MIC)의 인터럽트단(

)이 연결되도록하고, 상기 버스드라이버(BD)의 입력단(D1)에 3스테이트 디플립플롭(3DF)의 출력단(Q)을 접속하며 상기 마이크로프로세서(MIC)의 데이타버스(D0-D7)사 상기 3스테이트디플립플롭(3DF)의 입력단에 연결하고, 상기 프로그램어블인터버라이머(PIT)의 출력단(OUT1)에 인버터(N2)를 연결하여 디플립플롭(DF)의 클럭단(CK)에 연결하며 상기 디플롭플롭(DF)의 출력단(

)이 상기 마이크로프로세서(MIC)의

에 연결하고, 상기 마이크로프로세서(MIC)에서 발생하는 어드레스신호(A0-A4)를 디코더(DEC2)의 입력단(D)에 연결하고 상기 디코더(DEC2)의 출력단(Q1) 상기 3스테이트 디플립플롭(3DF)으 클럭단(CK)에 연결되고, 상기 마이크로프로세서(MIC)의 리세트단 (

)과 상기 디코더(DEC2)의 출력단(Q2)을 앤드게이트(AN1)의 입력단에 연결하고, 상기 앤드게이트(AN1)의 출력단을 상기 디플립플롭(DF)의 클리어단(CLR)에 연결하고 상기 프로그램어블 패리패럴 인터페이스회로(pp1)와 마이크로프로세서(MIC)가 버퍼 (U1-U4)를 연결한 구성이 중간제어기(13a-13d)중의 한 부분에 해당되며, 상기 제3도에서 데이타 흐름의 연결관계는 버퍼(U1-U4)를 통해 전달된다.3 is a relief circuit diagram between the main control unit 10 and the intermediate control units 13a-13d of FIG. 2 according to the present invention, and shows the data buses D0-D7 and the interrupt terminals (CPU) of the central processing unit (CPU).

Is connected to a programmable interrupt controller (PIC), a programmable interval timer (PIT) is connected from the programmable interrupt controller (PIC), and an input / output stage (I / OW) of the CPU. The data bus D0-D2 of the central processing unit CPU is connected to the input terminal of the decoder DE1, and the output terminals S1-S4 of the decoder DEC1 are the clock terminals of the JK flip-flops JF1-JF4. CK), the output terminal Q of the JK flip-flop JF1-JF4 is connected to the input terminals D1-D4 of the bus transceiver BT, and the output terminals Q1-Q4 of the buffer transceiver BT. Is connected to the programmable parallel interface circuit PP1, and the configuration in which the clear terminal CLR of the JK flip-flop JF1-JF4 is connected to the output terminals Q1-Q4 of the bus driver BD 10), the inverter N1 is connected from the output terminal Q4 of the buffer transceiver BT to connect the interrupt terminal of the microprocessor MIC.

) Is connected to the input terminal D1 of the bus driver BD, and the output terminal Q of the three state flip-flop 3DF is connected to the data bus D0-D7 of the microprocessor MIC. 3 is connected to the input terminal of the state flip-flop (3DF), the inverter N2 is connected to the output terminal (OUT1) of the programmable inverter (PIT) and connected to the clock terminal (CK) of the flip-flop (DF) And the output terminal of the deflop-flop (DF)

) Of the microprocessor (MIC)

And an address signal A0-A4 generated by the microprocessor MIC to an input terminal D of the decoder DEC2, and an output terminal Q1 of the decoder DEC2. 3DF) is connected to a clock stage CK, and a reset stage of the microprocessor MIC

) And the output terminal Q2 of the decoder DEC2 are connected to the input terminal of the AND gate AN1, and the output terminal of the AND gate AN1 is connected to the clear terminal CLR of the flip-flop DF. The configuration in which the programmable parallel interface circuit (pp1) and the microprocessor (MIC) connect the buffers (U1-U4) corresponds to one of the intermediate controllers (13a-13d). The relationship is passed through buffers U1-U4.

)의 출력(SP) 파형이며, (4g)는 디코더(DEC2)의 출력단(Q2)의 출력(S10)파형이다.4 is an operational waveform diagram according to the present invention, where 4a is a waveform diagram of an output S1-S4 of a predetermined portion of an output terminal S1-S4 of the decoder DEC1, and 4b is a bus transceiver. The output S5 waveform diagram of the output terminal Q4 of (BT) is shown, (4c) is the output (S6) waveform of the ejector N1, and (4d) is the output terminal (3d) of the 3-state deflip-flop 3DF. Q is the output S7 waveform, 4e is the output S8 waveform of the output terminal OUT1 of the programmable interval timer PIT, and 4f is the output terminal of the flip-flop DF.

(4g) is the output (Sg) waveform of the output terminal (Q2) of the decoder (DEC2).

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4, in order to send a command and data from the main controller 10 to the intermediate controllers 13a-13d. After the command and data are output from the central processing unit (CPU) to the programmable parallel interface circuit (PPI) through the data bus (D0-D7), they are generated at the input / output stage (I / OW) of the central processing unit (CPU). The input signal of the data buses D0-D2 is inputted to the decoder DEC1 according to the signal, and the signal S4 of the output terminals S1-S4 is the same as (4a) by decoding, so that the JK flip-flop JF1 When input to the clock terminal CK, the output of the output terminal Q becomes high at the negative edge of the 4c, and an interrupt signal is generated through the output terminal Q4 of the bus transceiver BT as shown in (4b).

)으로 인가된다. 이때 상기 마이크로프로세서(MIC)는 인터럽트가 발생되므로 인터럽트 루틴을 실행한다.The interrupt signal is input to the programmable parallel interface circuit PPI and is inverted by being input to the inverter N1. The inversion signal is output as shown in (4c) to be used as the microcontroller of one of the intermediate controllers 13a to 13d. Interrupt stage of the processor (MIC)

Is applied. At this time, the microprocessor MIC executes an interrupt routine because an interrupt is generated.

The programmable parity panel interface circuit (PPI) receiving the output interrupt signal of the bus transceiver (BT) generates a data transfer control signal and is applied to the clock terminals of the buffers (U1 and U2) to synchronize the clock to the programmable parity panel interface. Command data generated from the circuit PPI is latched in the buffer U1 and input to the microprocessor MIC, and control data is latched in the buffer U2 and input to the microprocessor MIC.

The microprocessor (MIC) interprets the command and data according to the interrupt routine, and executes a program according to the command to request data from the main controller 10 and is output according to a signal generated from the microprocessor (MIC). The data is transferred to the programmable parity interface circuit PPI through the buffers U3 and U4, and the central processing unit CPU pulls the output stage Q4 of the bus transceiver BT low by the output of the decoder DEC1. When it is set to the state, interrupt execution is completed, and at this time, the data of the buffers U3 and U4 are read and transmitted to the central processing unit (CPU) by the programmable parallel interface (PPI).

The microcontroller MIC of the intermediate controller outputs the data through one of the motor controllers 11a-11d and outputs the data from the D / A converter (not shown). Input to one motor controller of 11d).

When the main controller 10 transmits various commands or position data to the intermediate control unit 13 from the main control unit 13 to the various control units 13, the decoder DEC1 is used to make the (4a) signal an instantaneous low pulse. At this time, the high state of the bus transceiver BT, such as the signal (4d), is inverted in the inverter N1 to generate the signal (4c), and an interrupt is generated in the microprocessor (MIC) by this signal. This interrupt processing routine interprets the command of the main controller 10, executes the command, receives the next interrupt, and informs the main controller 10 of the completion of the interrupt. Make low-pulse output (Q) with (4d). By this signal, the signal of (4c) becomes high state and can receive the next interrupt. At this time, the main controller 10 reads the state of the programmable parallel interface circuit (PPI) to generate an interrupt on the next axis when the signal (4b) goes low or to recognize that the interrupt INT is performed in the intermediate controller.

From the programmable interval timer (PIT) of the main controller 10, the clock of 2ms period is supplied to the intermediate controller 13 as (4e). This signal reads the position data and status from the motor driver, Used to print

를 사용하였으며, 이 프로그램수행루틴에서 다음

를 수행하기 위해 디코더(DEC2)에 의해 (4g)와 같이 로우펄스를 출력한다.This is important because it's important to control the actual motor.

In this program execution routine,

The low pulse is output by the decoder DEC2 as shown in (4g).

)를 주제어기에서 제어하기 때문에 주제어기의 프로그램 수행시간과는 무관하고, 각축 콘트롤러가 서로 무관하므로 A/S가 용이하고, 각축의 위치를 동시제어가 가능한 이점이 있다.As described above, accurate timing can be supplied, so precise control is possible, and by distributing various functions of the main controller to the intermediate controller, it is easy to insert other application functions into the main controller, and interrupt (

) Is controlled by the main controller, so it is not related to the program execution time of the main controller, and since each controller is independent of each other, A / S is easy and the position of each axis can be controlled simultaneously.

Claims (1)

In the multi-axis control circuit of the robot, a main controller 10 for generating a control data by executing a program according to the multi-axis control of the robot, an AC servo motor 12a-12d for controlling each axis of the joint, and the AC servo motor The motor controllers 11a-11d for controlling 12a-12d and the interrupt signal generated by the main controller 10 execute an interrupt routine to interpret the command of the main controller 10 to interpret the command. And an intermediate controller (13a-13d) for generating the control data and converting the analog signal into an analog signal and then transferring the control data to the motor controller (11a-11d).

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