KR970004495B1 - Process for manufacturing semiconductor light switch - Google Patents
Process for manufacturing semiconductor light switch Download PDFInfo
- Publication number
- KR970004495B1 KR970004495B1 KR1019930018267A KR930018267A KR970004495B1 KR 970004495 B1 KR970004495 B1 KR 970004495B1 KR 1019930018267 A KR1019930018267 A KR 1019930018267A KR 930018267 A KR930018267 A KR 930018267A KR 970004495 B1 KR970004495 B1 KR 970004495B1
- Authority
- KR
- South Korea
- Prior art keywords
- type
- layer
- waveguide
- electrode
- spreading
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 title claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract 3
- 230000003287 optical effect Effects 0.000 claims description 38
- 230000000903 blocking effect Effects 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000005253 cladding Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000003892 spreading Methods 0.000 abstract 4
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000001802 infusion Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 8
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 239000011701 zinc Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/8605—Resistors with PN junctions
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Optical Integrated Circuits (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
제1a도 및 제1b도는 종래의 내부전반사형 반도체 광스위치의 평면도 및 단면도.1A and 1B are plan and cross-sectional views of a conventional internal reflection type semiconductor optical switch.
제2a도 및 제2b도는 본 발명의 내부전반사형 반도체 광스위치 구조의 평면도 및 단면도.2A and 2B are a plan view and a cross-sectional view of the internal reflection type semiconductor optical switch structure of the present invention.
제3도는 본 발명의 실시예에 따른 광스위치의 제작 공정 단계별 반사영역의 단면도.3 is a cross-sectional view of the reflective area for each step of the manufacturing process of the optical switch according to the embodiment of the present invention.
제4도는 본 발명의 변형예에 따른 내부전반사형 반도체 광스위치 구조의 단면도.4 is a cross-sectional view of an internal reflection type semiconductor optical switch structure according to a modification of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1 : n+-InP기판2 : n-InGaAsP 광도파로층1: n + -InP substrate 2: n-InGaAsP optical waveguide layer
2' : p--InGaAsP 광도파로층3 : n-InP클래드(clad)층2 ': p--InGaAsP optical waveguide layer 3: n-InP clad layer
4 : p-InP블로킹(blocking)층5 : n-InP캡(cap)층4: p-InP blocking layer 5: n-InP cap layer
6 : n--InGaAsP캡(cap)층7 : p형 전극6: n - InGaAsP cap layer 7: p-type electrode
8 : n형 전극9 : 아연(Zn)8 n-type electrode 9: zinc (Zn)
10 : 제1광입력포트11 : 제2광입력포트10: first optical input port 11: second optical input port
12 : 제1광출력포트13 : 제2광출력포트12: first optical output port 13: second optical output port
본 발명은 전류주입에 의한 광도파로의 굴절율의 변화를 이용한 내부전반사형 광스위치의 제조방법에 관한 것이다. 내부 전반사형 반도체 광스위치의 동작원리는 전류가 주입되면 광도파로층의 굴절율이 변하게 되는(감소하게 되는) 효과를 이용하는 것으로, 광도파로층의 소정영역으로 전류가 주입되면 전류가 주입된 영역과 주입되지 않은 영역사이에 굴절율의 차가 생기게 되고 이 굴절율 차에 의해 도파로를 따라 진행하던 빛이 스넬(Snell)의 법칙에 따라 전류주입 경계면에서 전반사를 일으키므로써 광진행 경로가 바뀌게 되어 스위칭이 일어나게 된다.The present invention relates to a method for manufacturing an internal reflection type optical switch using a change in refractive index of an optical waveguide by current injection. The operation principle of the total internal reflection type semiconductor optical switch utilizes the effect that the refractive index of the optical waveguide layer changes (reduces) when current is injected, and when the current is injected into a predetermined region of the optical waveguide layer, the current is injected and There is a difference in refractive index between the unrestricted regions, and the light traveling along the waveguide causes total reflection at the current injection interface according to Snell's law.
즉 전반사를 일으키는 굴절율 차를 얻기 위하여 일정량 이상의 전류주입이 요구되는데 이때 필요한 전력은 P=IV=I2R로서 R에 의하여 전력손질이 비례하게 된다.That is, a certain amount of current injection is required in order to obtain a refractive index difference that causes total reflection. The power required is P = IV = I 2 R, and power loss is proportional to R.
지금까지 발명된 내부전반사형 반도체 광스위치중에서 가장 대표적인 구조가 제1도에 있다.The most representative structure of the internal reflection type semiconductor optical switch invented so far is shown in FIG.
제1a도는 평면도이며, 제1b도는 제1a도에서 A 와 A' 방햐으로 절단하였을 때의 단면도이다.FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along the line A and A 'in FIG. 1A.
n형 InP기판(1)위에 InP기판과 격자 정합을 이루는 n형 InGaAsP광도파로층(2), n형 InP클래드층(3) 및 InP기판과 격자 정합을 이루는 n형 InGaAsP캡층(6)을 에피택시(epitaxy)법에 의해 순차적으로 성장시킨 후, (9)번영역에 아연(Zn)을 확산시켜 이 부분을 p형으로 만든다.An n-type InGaAsP optical waveguide layer (2) forming a lattice match with an InP substrate (2), an n-type InP cladding layer (3) and an n-type InGaAsP cap layer (6) making a lattice match with an InP substrate are epitaxially deposited on the n-type InP substrate (1). After sequentially growing by the taxi method, zinc (Zn) is diffused into region (9) to make this portion p-type.
그리고 InGaAsP캡층(6) 및 InP클래드층(3)을 식각하여 마루(ridge)형태의 광도파로 구조를 형성한 후 전류주입을 위한 전극(7)번 및 (8)번을 반도체와 저항성 접촉을 이루는 금속을 증착하여 형성한다.Then, the InGaAsP cap layer 6 and the InP cladding layer 3 are etched to form a ridge type optical waveguide structure, and then electrodes 7 and 8 for current injection are in ohmic contact with the semiconductor. It is formed by depositing a metal.
이와같이 제작된 광스위치에 입력포트(10)을 통하여 입사된 빛은 마루형태의 광도파로층(2)을 따라 진행하게 된다.The light incident through the input port 10 to the optical switch fabricated as described above proceeds along the optical waveguide layer 2 having a floor shape.
이때, 신호전류 주입을 위한 전극(7)과 (8) 사이에 신호 전류를 주입하지 않으면 광도파로층(2)에 아무런 굴절율의 변화가 없으므로 빛은 광도파로층(2)의 교차점을 직진 통과하여 제2출력포트(13)를 통하여 나오게 된다.At this time, if no signal current is injected between the electrodes 7 and 8 for signal current injection, there is no change in the refractive index of the optical waveguide layer 2, so the light passes straight through the intersection point of the optical waveguide layer 2. It exits through the second output port 13.
그러나 (7) 와 (8)번 전극사이에 순방향 전압을 걸어 전류가 흐르도록 하면 주입된 반송자(carrier)들이 모여 있는 p형의 클래드영역(3) 아래부분의 광도파로층(2)만 굴절율이 감소하게 되고, 이 굴절율 감소량이 스넬의 범칙에 따라 다음식을 만족하게 되면 이 부분에서 빛의 전반사가 일어나 빛은 제1출력포트(12)로 나가게 된다.However, if the current flows by applying a forward voltage between electrodes (7) and (8), only the optical waveguide layer 2 under the p-type cladding region 3 where the injected carriers are gathered has a refractive index. When the refractive index reduction amount satisfies the following equation according to Snell's law, total reflection of light occurs in this portion, and the light goes to the first output port 12.
△n≥n(1-cosθ)Δn≥n (1-cosθ)
여기에서, n은 광도파로층의 굴절율이고, △n은 전류주입에 의한 광도파로층의 굴절율변화량이며, θ는 진행하는 빛의 굴절율 변화영역(p형전극(7)의 아래부분)에 대한 반사 각도이다.Here, n is the refractive index of the optical waveguide layer, Δn is the amount of change in the refractive index of the optical waveguide layer by current injection, θ is the reflection on the refractive index change region (lower portion of the p-type electrode 7) of the light to proceed Angle.
제1도에서 보듯이 기존의 광스위치의 경우에는 도파로 부분안에서 Zn확산이 이루어져야 하고, 또한 Zn확산 부분안에서 p-전극(7)이 형성되어짐으로써 제작상에서 도파로폭과 옴접촉면적을 줄이는데 제한이 주어지게 된다.As shown in FIG. 1, in the conventional optical switch, Zn diffusion must be performed in the waveguide portion, and p-electrode 7 is formed in the Zn diffusion portion, thereby limiting the reduction in waveguide width and ohmic contact area in manufacturing. You lose.
본 발명의 목적은 도파로폭의 설계를 자유롭게 할 수 있는 반도체 광스위치의 제조방법을 제공하는 것이다.An object of the present invention is to provide a method of manufacturing a semiconductor optical switch that can freely design the waveguide width.
이제부터 첨부된 도면을 참조하면서 본 발명에 대해 상세히 설명하겠다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2a도는 본 발명에 따른 광스위치 소자의 평면도이고, 제2b도는 제2a도의 A-A'방향으로 절단한 단면도이다.FIG. 2A is a plan view of the optical switch element according to the present invention, and FIG. 2B is a cross-sectional view taken along the line AA ′ of FIG. 2A.
이와같은 구조를 갖는 광스위치 소자의 구체적 실시에는 다음과 같으며, 각 공정단계별 반사면 부분의 단면도가 제3도에 나타내었다.Specific implementation of the optical switch element having such a structure is as follows, and a cross-sectional view of the reflecting surface portion of each process step is shown in FIG.
n형 InP기판(1)위에 n형 InGaAsP 광도파로층(2)과, n형 InP 클래드층(3), 전류차단을 위한 p형 InP블로킹 층(4) 및, n형 InP캡층(5)을 MOCVD 또는 LPE에 의한 에피택시(epitaxy)법으로 순차적으로 성장시키다(제3도(a)).An n-type InGaAsP optical waveguide layer 2, an n-type InP cladding layer 3, a p-type InP blocking layer 4 for blocking current, and an n-type InP cap layer 5 are disposed on the n-type InP substrate 1; Growing sequentially by epitaxy method by MOCVD or LPE (Fig. 3 (a)).
그리고 반사면을 이루는 부분의 n형 InP캡층(5)을 홈(groove) 모양으로 식각한 후에(제3도(b)) 전면에 Zn확산을 시킨다(제3도(c)).Then, the n-type InP cap layer 5 forming the reflective surface is etched into a groove shape (FIG. 3 (b)), and then Zn diffusion is performed on the entire surface (FIG. 3C).
반사면을 이루는 부분에 p형 전극(7)을 증착하고(제3도(d)) 상기 광도파로층(2)위의 각층을 습식 또는 건식식각법에 의해 식각해낸 후에 n형 전극(8)을 증착한다(제3도(e)).The p-type electrode 7 is deposited on the part forming the reflective surface (FIG. 3 (d)), and each layer on the optical waveguide layer 2 is etched by wet or dry etching, and then the n-type electrode 8 Is deposited (FIG. 3 (e)).
이와같이 제작된 광스위치는 제3도(e)에서 보듯이 전극면의 폭이 Zn확산부분 보다 넓게되어 p형 접촉저항을 줄일 수 있게 된다.In the optical switch fabricated as described above, as shown in FIG. 3E, the width of the electrode surface is wider than that of the Zn diffusion portion, thereby reducing the p-type contact resistance.
Zn확산부분 옆의 p형 전극(7)아래는 p/n/p/n 접합이 형성되어 전류가 차단되어져 반사면에만 효과적인 전류주입이 이루어지고 접촉면적을 극대화시키게 되는 것이다.Under the p-type electrode 7 next to the Zn diffusion, a p / n / p / n junction is formed so that the current is cut off so that effective current injection is made only on the reflective surface and the contact area is maximized.
제4도는 본 발명의 변형된 예로서 도파로의 p형의 InGaAsP일 경우이다.4 is a modified example of the present invention when the p-type InGaAsP of the waveguide.
이 경우에는 제2도의 경우와 달리 전류차단층인 p-InP가 따로 삽입되지 않는 구조로 접촉저항의 극대화가 가능한 구조이다.In this case, unlike the case of FIG. 2, the contact resistance is maximized because the current blocking layer p-InP is not inserted separately.
이상에서 설명된 바와같이 본 발명에 의하면 다음과 같은 효과를 얻을 수 있다.As described above, according to the present invention, the following effects can be obtained.
-p옴 저항접촉면적을 극대화시켜 접촉저항을 최소화 시킨다.-Maximize contact resistance by maximizing pohm resistance contact area.
-종래 구조의 경우에 전극 증착시의 리쏘그라피 정렬이 약 1㎛ 이내로 요구되나 본 발명의 경우에는 이러한 제한 요수가 사라진다.In the case of conventional structures, lithographic alignment at the time of electrode deposition is required within about 1 μm, but in the case of the present invention this limiting factor disappears.
-종래의 경우에는 도파로 부분안에 반사면을 이루는 확산 영역이 들어가야하고 또한 확산영역안에 적극부분이 들어 가야하는 등의 제한요건으로 도파로 폭의 제한이 있게 된다.-In the conventional case, the waveguide width is limited because the diffusion region forming the reflecting surface should enter the waveguide portion and the active portion should enter the diffusion region.
그러나 본 발명의 구조에서는 확산이 전면에 걸쳐서 이루어지고 전극이 반사면을 이루는 지점의 도파로 전면에 형성됨으로 제작상의 제한요소를 제거시켜 도파로 폭의 설계를 자유롭게 할 수 있다.However, in the structure of the present invention, the diffusion is made over the entire surface and the electrode is formed on the front side of the waveguide at the point where the electrode forms the reflective surface, thereby eliminating manufacturing limitations and freeing the design of the waveguide width.
-상기한 효과들에 의해 광스위치 제작조건을 완화시켜 모듈의 제작비용을 절감할 수 있다.The above-described effects can be alleviated the manufacturing conditions of the optical switch to reduce the manufacturing cost of the module.
Claims (3)
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930018267A KR970004495B1 (en) | 1993-09-10 | 1993-09-10 | Process for manufacturing semiconductor light switch |
| US08/301,998 US5581108A (en) | 1993-09-09 | 1994-09-07 | Optical Switching device |
| DE4432010A DE4432010C2 (en) | 1993-09-09 | 1994-09-08 | Optical switching device and manufacturing method therefor |
| GB9418153A GB2281786B (en) | 1993-09-09 | 1994-09-08 | Optical switching device and manufacturing method of the same |
| FR9410930A FR2709842B1 (en) | 1993-09-09 | 1994-09-08 | Optical switching device and method of manufacturing such a device. |
| JP6216322A JP2792826B2 (en) | 1993-09-09 | 1994-09-09 | Optical switch and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930018267A KR970004495B1 (en) | 1993-09-10 | 1993-09-10 | Process for manufacturing semiconductor light switch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950010147A KR950010147A (en) | 1995-04-26 |
| KR970004495B1 true KR970004495B1 (en) | 1997-03-28 |
Family
ID=19363351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930018267A KR970004495B1 (en) | 1993-09-09 | 1993-09-10 | Process for manufacturing semiconductor light switch |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970004495B1 (en) |
-
1993
- 1993-09-10 KR KR1019930018267A patent/KR970004495B1/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| KR950010147A (en) | 1995-04-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4840446A (en) | Photo semiconductor device having a multi-quantum well structure | |
| EP0543369B1 (en) | Modulator or switch with vertically-coupled anti-resonant reflecting optical waveguides ("arrow") on silicon | |
| JPS643078B2 (en) | ||
| JPH0685035B2 (en) | Light switch | |
| US6072812A (en) | Distributed feedback laser with loss coupling | |
| KR970004495B1 (en) | Process for manufacturing semiconductor light switch | |
| US5581108A (en) | Optical Switching device | |
| KR0155509B1 (en) | The fabrication method of opto-electronic ic | |
| KR950009631B1 (en) | Internal total reflection type semiconductor optical switch | |
| US5048039A (en) | Laser diode | |
| JPH06130236A (en) | Cross type optical switch | |
| KR970008342B1 (en) | High speed switch manufacturing method to ion injection | |
| KR970006608B1 (en) | Method of manufacturing optical switch | |
| KR950009632B1 (en) | Semiconductor optical switch apparatus | |
| KR970011524B1 (en) | Manufacturing method of inner full reflection type optical switch using trench | |
| KR970006607B1 (en) | Method of manufacturing high speed optical switch | |
| JPS6329596A (en) | Semiconductor laser | |
| KR100212000B1 (en) | Swmiconductor optical tunable filter having wavelength selectivity and method for fabricating the same | |
| JPS6318874B2 (en) | ||
| JPS57139984A (en) | Buried photo emitting and receiving semiconductor integrated device | |
| JPH0548889B2 (en) | ||
| JPS60173519A (en) | Semiconductor optical switch | |
| JPH02298923A (en) | Semiconductor optical switch | |
| JPH023024A (en) | Semiconductor optical switch | |
| JPS5858783A (en) | Semiconductor laser |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| N231 | Notification of change of applicant | ||
| G160 | Decision to publish patent application | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |