KR970004417A - Message Receiving Method and Circuit in Wireless Pager - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

A method for receiving a message in a pager, in particular RF, which is continuous during deployment even when a sync detection or preamble detection fails for a time and detects a sync code to receive a message.

2. The technical problem to be solved by the invention

The present invention provides a circuit and a method for detecting batch data by detecting successive sync codes when it is confirmed that a batch is detected by other means even if preamble or sync code detection fails during RF reception on time as a method of saving power.

3. Summary of the Solution of the Invention

In the method of receiving a message of a wireless pager, the preamble detection process for detecting whether the preamble is received by resetting the power, and the sync is detected when the preamble is not detected in the second process, and whether the BCH code format is matched when the preamble is not. A method of receiving a message in a wireless pager, comprising: detecting a BCH code format checking process; and processing an address message when a sink is detected in the BCH code format checking process, but processing until the end of the batch. .

4. Important uses of the invention

Message receiver of radio pager.

Description

Message Receiving Method and Circuit in Wireless Pager

Since this is an open matter, no full text was included.

4 is a circuit diagram according to the present invention, 5 and 6 are flowcharts according to the present invention, and FIG. 7 is a timing diagram according to the present invention.

Claims (8)

In the message receiving circuit of the pager, the first buffer 111 buffers 31 bits of the codeword of the received data according to the clock of the clock stage 102, and 31 pieces are counted by the clock of the clock stage 102. A data detector 131 for outputting "0" when both the first counter 112 and the first buffer 111 buffering the input of the data input terminal 101 are "0" or "1"; The AND gate 117 for inputting the clock of the clock stage 103 according to the output of the first counter 112, and the AND gate 117 by loading parallel codeword data buffered in the first buffer 111. The first shift register 113 shifts to a clock output from the first shift register 113, and the first shift register 113 receives the output code word and divides the BCH decoding into a first minimum polynomial from a signed polynomial. 114) and an output codeword of the first shift register 113 in a code polynomial. A second syndrome calculation unit 115 for BCH decoding by dividing into a second minimum polynomial, a detection means for detecting a BCH code error from the outputs of the first and second syndrome calculation units 114 and 115, and the first syndrome calculation. Selection means for selecting an output thereof when the output of the unit 114 is not " 0 " (S1) ³ calculation unit 116 for trigonalizing the output of the selection means, the first syndrome calculating unit 114; and, RF enable signal for generating an output (S3) and the RF enable signal for the comparison means, the battery saving for comparing an output of the (S1) ³ calculator 116 of the second syndrome calculation unit 115 Initialization signal generating means for generating a reset initialization signal by means of compensation means, an output of said first syndrome calculating section 114, and an output of said comparing means, and said RF enable signal from an output of said detecting means and comparing means. Generation of a presetting signal for generating a presetting signal of the generating means End, wherein the RF receiving messages in a radio pager, characterized by consisting of a battery saving controller (125) for generating a clear signal of the enable signal generating circuit means. 2. The message receiving circuit of claim 1, wherein the detecting means comprises an oragate (120). 3. A message receiving circuit according to claim 2, wherein said selecting means comprises an end gate (119). 2. A message receiving circuit according to claim 1, wherein said selecting means comprises an exclusive oracle (122). 2. The message receiving circuit according to claim 1, wherein the initialization signal generating means comprises a NAND gate (123). 2. The message receiving circuit according to claim 1, wherein the presetting signal generating means comprises an end gate (121). In the method of receiving a message of a pager, a preamble detection process for detecting whether or not a preamble is received by resetting the power, and a sync when the preamble detection is not detected in the second process, and whether the BCH code format is matched when the preamble is not detected. And a message processing process of processing an address message when a sink is detected in the BCH code format checking process and processing until a batch is last. 8. The method of claim 7, wherein the BCH code format checking process comprises: a first process of checking a 31-bit input; and a second process of loading the 31 bits of the first process and calculating first and third syndromes by BCH decoding to detect an error; When the first and third syndromes of the second process are all zero, the RF is continuously turned on to find synchronization, and when the first syndrome is not "0", the first syndrome is trigonometry (S ₁ ) ^3. A third step of checking whether the third syndrome value (S ₁ ) is matched, and in the third step, when (S ₁ ) ³ and S3 coincide with each other, RF is continuously turned on to find synchronization and a bit is not matched. And a fourth process of clearing the buffer after the shift. ※ Note: The disclosure is based on the initial application.