KR0168787B1 - Circuit and method of message receiving in wireless pager - Google Patents

Abstract

1. Field of the invention as claimed in the claims: relates to a method of receiving a message in a pager, in particular, a method of receiving a message by detecting a sync code continuous during the batch even in the case of failure to detect the sink or preamble during the RF-on time .

2. The technical problem to be solved by the invention: Even if the preamble or sync code detection fails during the RF reception on time as a method of saving power, if it is confirmed that the batch by other means to detect the continuous sync code to detect the batch data Provides circuits and methods that can be used.

3. Summary of the solution of the invention:

In the method of receiving a message of a wireless pager, a preamble detection process for detecting whether or not a preamble is received by resetting the power, and a sync is detected when the preamble is not detected in the second process, and whether the BCH code format is matched when the preamble is not. And a message processing process of processing an address message when a sink is detected in the BCH code format checking process and processing until a batch is last.

4. Significant use of the invention: Message receiver for radio pagers

Description

Message Receiving Method and Circuit in Wireless Pager

1 is a diagram of a conventional radio calling system.

2 is a received data format diagram for explaining an embodiment of the present invention.

3 is a conventional wireless reception flowchart.

4 is a circuit diagram according to an embodiment of the present invention.

5 and 6 are flowcharts in accordance with an embodiment of the present invention.

7 is a timing diagram according to an embodiment of the present invention.

The present invention relates to a method of receiving a message in a wireless pager, and more particularly, to a method of receiving a message in a wireless pager capable of receiving a message by detecting a continuous sync code during deployment even when a sink detection or preamble detection fails during an RF on time; It is about a circuit. In general, the wireless call receiver receives and analyzes a specific type of wireless call information and performs a function of alerting the call information at a time related to itself. 1 shows the overall configuration of a radio page receiver. Referring to FIG. 1, the receiver 11 receives radio call information and performs functions of frequency conversion, demodulation, and waveform shaping. Therefore, the output of the receiver 11 becomes information according to a radio call converted into digital data. The output of the receiver 11 is applied to the decoder 12. The decoder 12 decodes the received data and sets an operation mode of the radio page receiver. That is, in the idle mode, the operation power is controlled to be supplied at regular intervals to detect the preamble data, and in the batch mode, the word sync data and the set frame data are detected. The detected frame data is decoded and converted into the original data form. The microcontroller 15 receives the decoded data output from the decoder unit 12. The microcontroller 15 processes the received data to control an alarm function. The alarm unit 18 generates an alarm signal such as a tone signal or a vibration signal for informing that the alarm unit 18 has been called by the alarm control signal output from the microcontroller 15. The display unit 17 displays the message of the calling party and the status information of the radio call receiver by the display control signal output from the microcontroller 15. The memory 16 stores unique address information and frame information assigned to the radio page receiver. In addition, referring to FIG. 2, the form of the POCSAG code used in the above-mentioned radio call receiver is generated as shown in (2a) of FIG. One POCSAG code consists of preamble data consisting of 576 bits and a plurality of batch data contiguous as shown in (2b) of FIG. The preamble data is a reversal code in which 1 and 0 are repeated for 576 bits. The one POCSAG code usually consists of 30 batches up to 60 batches. One arrangement consists of one word sync data of 32 bits and eight frame data of 64 bits as shown in FIG. 2C. Here, the word sync data is 32-bit data of (7CD215D8) H and (0111110011010010000101011101100) B as shown in 2d of FIG. Each frame data is composed of 32 bits of address code word and 32 bits of message code word as shown in FIG. 2E. Therefore, one arrangement is composed of 17 words of 544 bits of data (17 words * 32 bits = 544 bits) in which 32 bits of data are one word as shown in FIG. 2C. Therefore, the radio call terminal performs transmission and reception data processing by detecting the preamble information transmitted and received at a predetermined time (constant bit) for the purpose of saving power. However, in the prior art, due to noise and other factors, the transmitted data state is in a batch mode unless the preamble information is captured and the sync code is not accidentally caught as shown in FIG. There was a problem that could not process all the batch data that followed. Therefore, an object of the present invention is being deployed by other means even if the radio call terminal fails to detect the preamble or sync code during the RF reception on time by a method of turning on / off the RF information reception enable end in a power saving manner. If this is confirmed, the present invention provides a circuit and a method for detecting batch data by detecting consecutive sync codes. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

4 is a BCH decoder circuit diagram of the decoder according to the present invention. The first buffer 111 buffers 31 bits of the codeword of the data input terminal 101 according to the clock of the clock stage 103, and the clock stage 103. Data counting unit 131 outputting 0 when the first counter 112 counts 31 by a clock and the first buffer 111 buffers the input of the data input terminal 101 at zero or one. ), An AND gate 117 for inputting a clock of the clock terminal 141 according to the outputs of the data detector 131 and the first counter 112, and a parallel codeword buffered by the first buffer 111. The first shift register 113 for loading data and shifting the clock to the clock output from the AND gate 117 and the output code word of the first shift register 113 are received and divided into a first minimum polynomial from a sign polynomial and a BCH. A first syndrome calculator 114 for decoding and the first shift register A second syndrome calculation unit 115 for receiving the output codeword of 113 and dividing the code polynomial into a second minimum polynomial and performing BCH decoding, and whether the BCH code error is detected from the outputs of the first and second syndrome calculation units 114 and 115; Received the output of the oragate 12 to detect, the output of the first syndrome calculation unit 114 and the gate (119) to select its output when the output of the first syndrome calculation unit 114 is not 0 to cube the output of the aND gate (119) (S _1), ^third calculating unit 116, the first output of the second syndrome calculation unit (115) (S ₁₎ ³ wherein (S _1), ^third calculating unit (116 Exclusive oar gate 122 to compare the output of the), the de-flop 124 for generating an RF enable signal for battery saving, the output of the first syndrome calculator 114 and the exclusion by sieve Iowa output of gate 122 occurs the initialization signal of the first shift register 113 and (S ₁₎ ³ calculator 116 An AND gate 121 for generating a pre-setting signal of the deflip-flop 124 from the NAND gate 123, the output of the oragate 120, and the exclusive occupancy 122, and the deflip The battery saving controller 125 generates a clear signal of the flop 124.

5 is a flowchart of BCH code format determination according to the present invention. The preamble detection process detects whether a preamble is received by resetting the power supply, and the sink is detected when the preamble is not detected in the detection process. A BCH code format checking process for detecting a code format match and a message processing process for processing an address message when a sink is detected in the BCH code format checking process until the arrangement is last.

FIG. 6 is a detailed flowchart of the BCH code format checking process of FIG. 4 according to the present invention. The first process of checking a 31-bit input and the 31-bit of the first process are loaded, and the first and third syndromes are loaded by BCH decoding. The second process of calculating an error and the first and third syndrome calculation values of the second process are all zeros, and the RF is continuously turned on to find synchronization. When the first syndrome is not zero, the third syndrome is squared ( S1) ³ to confirm whether the third syndrome value (S3) is matched with the third process, and when the (S1) ³ and the third syndrome value (S3) in the third process is consistent with the RF on the synchronization When a match is not found, a fourth process of clearing the buffer after shifting one bit is performed.

7 is an RF enable timing diagram of the def flip-flop 124 according to the present invention.

(7a) is a waveform code data waveform diagram, (7b) is a data processing timing diagram according to the power saving operation of the pager, (7c) is an RF enable timing diagram of the data stream when the preamble detection fails, (7d ) Is an operational waveform diagram showing an embodiment of the present invention.

In (7b), operation ① indicates a preamble detection process in which 1010 ... is repeated for 576 bits, ② represents an operation of finding the first first sync code of 7CD215D8, and ③ represents operation of ① and ②. When there is no error in the operation, the terminal searches for the magnetic address and the message in a predetermined frame based on the magnetic address code. ④ shows the repetitive operation of finding the second, third, ... sync codes. (7c) is an RF enable timing diagram of the data stream in which preamble detection is repeated by repeating ① and ② of (7b) in the absence of received data. In the state where the preamble is not detected, the timing is repeated according to the period of the RF1 enable, and the synchronization code is almost impossible to detect.

(7d) shows an example of timing implemented in the embodiment of the present invention, wherein the state of operation ① 'in the same state as the above (7C) is in addition to the preamble and sync code detection operation for the data received during the RF enable. By determining whether the data is based on the BCH code format, when the third preamble of (7d) is matched with the BCH code format, operation (1) of (7b) is performed to detect the sync code in the arrangement. Make it possible. Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS. 1 to 7, and the received signal through the receiving unit is input to the data input terminal 101 of the decoder and according to the clock of the clock terminal 103, the first buffer. It is inputted at 111 and buffered. When all of 0's or 1's are input in the first buffer 111, the output of the data detector 131 becomes 0 '. At this time, the output of the AND gate 117 is also zero. On the other hand, the output parallel 31 bits of the first buffer 111 is serially converted by the clock in accordance with the output signal of the AND gate 117 in the first shift register 113 is output. The output of the first shift register 113 is input to the first and second syndrome calculators 114 and 115. The first shift register 113 is synchronized with the clock of the clock terminal CLOCK2 141, and the clock of the clock terminal CLOCK2 for the shift is applied to the first and second syndrome calculators 114 and 115. The first and second syndrome calculation units 114 and 115 calculate the generation polynomial q (x) = x ¹⁰ + x ⁹ + x ⁸ + x ⁶ + x ⁵ + x ³ +1 of the BCH (31,21) code. , Which is the product of least polynomial m ₁ (x) = 1 + x ² + x ⁵ , m ₃ (x) = 1 + x ² + x ³ + x ⁴ + x ⁵ m ₁ (x), m ₃ (x) S1 of the first syndrome calculation unit 114 is the remainder obtained by dividing the sign polynomial C (X) by m ₁ (x) and dividing the sign polynomial C (X) by m ₃ (x). The error position polynomial of the BCH (31,21) code is o (x) = 1 + S ₁ x + (S ₁ ² + S ₃ / S ₁ ) X ² [S ₁ ≠ 0, S ₃ ≠ S ₁ ³ ]. If S ₁ = 0 of the _{first and} second syndromes 114 and 115 and S ₃ = 0, there is no o (x) = 1 error, and if S ₁ ≠ 0 and S ₃ = S ₁ ^{3 of the} _first and second syndromes 114 and 115 If o (x) = 1 + S ₁ x single error and S ₁ ≠ 0 and S ₃ ≠ S ₁ ^{3 of the} _first and second syndromes 114 and 115 More than 2 bits are an error. That is, when the output terminal S ₁ of the AND gate 119 is not 0 from the outputs of the first and second syndrome calculating units 114 and 115, the output of the first syndrome calculating unit 114 is (S ₁ ) ^3. It is applied to the calculation unit 116 and multiplied by three. If the output S2 ³ of the second syndrome calculating unit 115 is not zero, it is one. The outputs of the first and second syndrome calculation units 114 and 115 are input to the oragate 120 to output S ₁ = 0 and S ₃ = 0 to determine that there is an error. The outputs of the second syndrome calculating unit 115 and the (S ₁ ) ³ calculating unit 116 are compared in the exclusive oar gate 122 so that S ₁ = 0, S ₃ ≠ 01 or S ₁ ³ = S ₃ The output is zero. When the outputs of the orifice 120 and the exclusive oar gate 122 become 0, the output of the AND gate 121 becomes 0, and the deflip-flop 124 is preset so that the output becomes 0. It enters economy mode. If the NAND gate 123 is S ₁ ³ ? S ₃ or S? 0, the output goes low to clear the parts. When S ₁ = 0 and S ₃ = 0 of the first and second syndrome calculation units 114 and 115, there is no error. If S ₁ ≠ 0 and S ₁ ³ ≠ S _{3, this} means a 1-bit error. This is explained sequentially in FIGS. 5 and 6. When the preamble detecting the preamble reception is detected in step 5b by resetting the power on in step 5a, the sink is detected in step 5d, and when the preamble is not detected in step 5b, step 5c. Detects whether the BCH code format matches and then detects the sync in step 5d. If the sink is detected in step 5d, the address message is processed in step 5e, and the process is processed until the arrangement is final in step 5f. The format checking process of the BCH code of FIG. 4 described in FIG. 6 confirms the 31-bit input in step (6a), loads 31 bits in step (6b), and then transfers the BCH decoding in step (6d, 6c). The error is detected by calculating the first and third syndromes. In operation (6e, 6f), it is calculated whether the first and third syndromes are all zero. When the first syndrome is not 0, the first syndrome is tripled (S1) ³ and the third syndrome value (S3) is checked in (6j). In step (6j), the RF is continuously turned on when it matches (S1) ³ and the third syndrome value (S3), and shifted by one bit in step (6g) when it does not match in step (6j). The buffer is cleared at step (6h), and if the first and third syndrome calculation values are all zero at step (6e, 6f), Rf continues to be found.

As described above, the present invention recognizes that the radio call terminal operates by using the third means even if the preamble or the sync code detection fails during the RF on time in the radio call terminal operating the RF on / off for the purpose of power saving. There is an advantage in that batch data can be processed by detecting with a sync code.

Claims (3)

In the message receiving circuit of the pager, the first buffer 111 buffers 31 bits of the codeword of the data input terminal 101 according to the clock of the clock stage 103, and the clock of the clock stage 103 is 31. A first counter 112 for counting the number of dogs, a data detector 131 for outputting 0 when the first buffer 111 buffers the input of the data input terminal 101 to 0 or 1, and the data The AND gate 117 for inputting the clock of the clock terminal 141 according to the output of the detector 131 and the first counter 112, and the parallel codeword data buffered in the first buffer 111 are loaded to A first syndrome that receives the first shift register 113 shifted to the clock output from the AND gate 117 and the output codeword of the first shift register 113, and divides the BCH decoding from the sign polynomial into the first minimum polynomial; An output code of the calculation unit 114 and the first sheep register 113; A second syndrome calculation unit 115 for receiving the code and dividing it into a second minimum polynomial from the sign polynomial by the second minimum polynomial, and the OG gate 120 for detecting the BCH code error from the outputs of the first and second syndrome calculation units 114 and 115. ), An AND gate 119 that selects an output thereof when the output of the first syndrome calculator 114 is not 0, and the AND gate 119 that receives the output of the first syndrome calculator 114. and in that the cube an output (S ₁₎ ³ calculator 116 compares the output of the second syndrome calculation unit 115, an output (S ₁₎ ³ and the (S ₁₎ ³ calculator 116 of Exclusive oar gate 122, a de-flop 124 for generating an RF enable signal for battery saving, the output of the first syndrome calculator 114 and the exclusive oar gate 122 ) by the output of NAND gate (123 to generate the initialization signal of the first shift register 113 and (S ₁₎ ³ calculator 116 in) And an AND gate 121 generating a presetting signal of the deflip-flop 124 from the outputs of the orifice 120 and the exclusive oar gate 122, and the clear signal of the deflip-flop 124. Message receiving circuit in a wireless pager, characterized in that consisting of a battery saving control unit (125) for generating a. In the method of receiving a message of a pager, a preamble detection process for detecting whether or not the preamble is received by resetting the power on the pager, and when the preamble is detected in the preamble detection process, the sink is detected and the preamble is detected. If not, the process of sync detection and BCH code format checking to detect whether the BCH code format, and when the sink is detected during the sync detection and BCH code format checking process to process the address until the end of the batch Message receiving method in a pager, characterized in that the message processing process. The method of claim 2, wherein the BCH code format checking process includes a first process of checking a 31-bit input of received data, and loads 31 bits of the first process into a buffer to calculate first and third syndromes by BCH decoding. The second process of detecting and the first and third syndrome calculation value of the second process is all 0 'temporary RF to continue to find the synchronization and the first syndrome when the first syndrome is not the third squared (S ₁₎ is calculated in ^three third syndrome value (S3) and match the third step to determine whether the third step in (S ₁₎ ³ and the third syndrome the RF continues to (S3) are matched And a fourth step of clearing the buffer after shifting 1 bit when the synchronization is not found and there is a mismatch.