KR970003755A - Wafer Orientation Inspection System - Google Patents

Wafer Orientation Inspection System Download PDF

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Publication number
KR970003755A
KR970003755A KR1019960020712A KR19960020712A KR970003755A KR 970003755 A KR970003755 A KR 970003755A KR 1019960020712 A KR1019960020712 A KR 1019960020712A KR 19960020712 A KR19960020712 A KR 19960020712A KR 970003755 A KR970003755 A KR 970003755A
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South Korea
Prior art keywords
wafer
orientation
crystallographic orientation
inspection system
processing system
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KR1019960020712A
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Korean (ko)
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KR100424545B1 (en
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에프. 란도 리차드
디. 슐띠스 에드워드
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제임스 엠 윌리암스
배리언 어소시에이츠 인코포레이티드
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Publication of KR970003755A publication Critical patent/KR970003755A/en
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Publication of KR100424545B1 publication Critical patent/KR100424545B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67796—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations with angular orientation of workpieces
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/90—Apparatus characterized by composition or treatment thereof, e.g. surface finish, surface coating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10T117/10—Apparatus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10T117/10—Apparatus
    • Y10T117/1004—Apparatus with means for measuring, testing, or sensing

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)

Abstract

진공을 파괴하지 않고 시스템 비가동 시간을 최소화하는 다중 스테이션 웨이퍼 처리 시스템의 이송 아암을 정확하게 조정하는 장치 및 방법이 제공된다. 또 웨이퍼가 처리 스테이션들 사이에서 이송하는 동안, 개별 웨이퍼의 배향을 감시할 뿐만 아니라 처리 전 웨이퍼의 결정학적 배향을 결정하고 적당하게 배열하는 시스템이 제공된다.An apparatus and method are provided for precisely adjusting the transfer arm of a multi-station wafer processing system without breaking the vacuum and minimizing system downtime. Also provided is a system for monitoring the orientation of individual wafers as well as determining and properly arranging the crystallographic orientation of the wafer prior to processing while the wafer is transferred between processing stations.

Description

웨이퍼 배향 검사 시스템Wafer Orientation Inspection System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명의 한 특징을 포함하는 처리 시스템을 간단히 도시하는 도면.4 is a simplified illustration of a processing system incorporating an aspect of the present invention.

Claims (9)

봉인가능한 반도체 처리 시스템에서 웨이퍼의 결정학적 배향을 검사하는 방법에 있어서, 상기 시스템이 봉인되는 동안 웨이퍼가 봉인가능한 반도체 처리 시스템에서 제1위치에서 제2위치까지 이송될때, 상기 웨이퍼의 결정학적 배향을 검출하는 단계와, 상기 웨이퍼의 결정학적 배향이 미리 선택된 결정학적 배향과 일치하는지의 여부를 결정하는 단계를 포함하는 것을 특징으로 하는 검사 방법.A method for inspecting the crystallographic orientation of a wafer in a sealable semiconductor processing system, the method comprising: determining a crystallographic orientation of the wafer when the wafer is transferred from a first position to a second position in a sealable semiconductor processing system while the system is sealed. Detecting and determining whether the crystallographic orientation of the wafer coincides with a preselected crystallographic orientation. 제1항에 있어서, 상기 검출 단계는 비디오 카메라에 의해 상기 웨이퍼를 원격으로 화상화하는 단계를 부가로 포함하는 것을 특징으로 하는 검사 방법.The method of claim 1, wherein the detecting step further comprises remotely imaging the wafer by a video camera. 제2항에 있어서, 상기 원격 화상 단계는 상기 웨이퍼의 결정학적 배향을 결정하는 컴퓨터로 웨이퍼의 화상을 통신하는 단계를 부가로 포함하는 것을 특징으로 하는 검사 방법.The method of claim 2, wherein the remote imaging step further comprises communicating an image of the wafer to a computer that determines the crystallographic orientation of the wafer. 제1항에 있어서, 상기 미리 선택된 결정학적 배향에 따라 웨이퍼의 결정학적 배향을 정렬하는 단계를 부가로 포함하는 것을 특징으로 하는 검사 방법.The method of claim 1, further comprising aligning the crystallographic orientation of the wafer according to the preselected crystallographic orientation. 봉인가능한 반도체 처리 시스템 내의 결정학적 배향을 검사하는 웨이퍼 배향 검사 시스템에 있어서, 상기 처리 시스템이 봉인되는 동안, 웨이퍼가 봉인가능한 반도체 처리 시스템에서 제1위치에서 제2위치까지 이송 경로를 통해 이송되는 동안, 웨이퍼의 배향을 결정하는 배향 감지 시스템과, 상기 배향 감지 시스템에 결합된 컴퓨터를 포함하며, 상기 컴퓨터는 웨이퍼의 상기 결정학적 배향이 미리 선택된 결정학적 배향과 일치하는지를 결정하는 것을 특징으로 하는 웨이퍼 배향 검사 시스템.A wafer orientation inspection system for inspecting crystallographic orientation in a sealable semiconductor processing system, wherein the wafer is transferred through a transfer path from a first position to a second position in a sealable semiconductor processing system while the processing system is sealed. An orientation sensing system for determining the orientation of the wafer, and a computer coupled to the orientation sensing system, wherein the computer determines whether the crystallographic orientation of the wafer matches a preselected crystallographic orientation Inspection system. 제5항에 있어서, 상기 배향 감지 시스템은 웨이퍼용 이송 경로에 인접한 위치에 장착된 비디오 카메라를 부가로 포함하고, 상기 카메라의 위치는 웨이퍼가 제1위치에서 제2위치까지 이송될때 상기 카메라로 웨이퍼를 관찰이 가능하게 하는 것을 특징으로 하는 웨이퍼 배향 검사 시스템.6. The system of claim 5, wherein the orientation sensing system further comprises a video camera mounted at a position adjacent the transfer path for the wafer, the position of the camera being transferred to the camera when the wafer is transferred from the first position to the second position. Wafer orientation inspection system, characterized in that to enable observation. 제6항에 있어서, 상기 비디오 카메라에 결합된 광각 렌즈를 부가로 포함하는 것을 특징으로 하는 웨이퍼 배향 검사 시스템.7. The wafer orientation inspection system of claim 6 further comprising a wide angle lens coupled to the video camera. 제5항에 있어서, 상기 컴퓨터는 상기 웨이퍼의 결정학적 배향이 미리 선택된 결정학적 배향과 일치하지 않을 경우 상기 웨이퍼용 식별 데이타를 기록하는 것을 특징으로 하는 웨이퍼 배향 검사 시스템.6. The wafer orientation inspection system of claim 5 wherein the computer records identification data for the wafer if the crystallographic orientation of the wafer does not match a preselected crystallographic orientation. 제5항에 있어서, 상기 봉인가능한 반도체 처리 시스템은 스퍼터링 시스템(sputtering system)인 것을 특징으로 하는 웨이퍼 배향 검사 시스템.6. The wafer orientation inspection system of claim 5 wherein the sealable semiconductor processing system is a sputtering system. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960020712A 1995-06-07 1996-06-05 Wafer orientation inspection system KR100424545B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US47523495A 1995-06-07 1995-06-07
US475234 1995-06-07
US475,234 1995-06-07

Publications (2)

Publication Number Publication Date
KR970003755A true KR970003755A (en) 1997-01-28
KR100424545B1 KR100424545B1 (en) 2004-06-18

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Publication number Publication date
US6120601A (en) 2000-09-19
KR100424545B1 (en) 2004-06-18
JPH09102530A (en) 1997-04-15

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