KR970003457A - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

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Publication number
KR970003457A
KR970003457A KR1019950015174A KR19950015174A KR970003457A KR 970003457 A KR970003457 A KR 970003457A KR 1019950015174 A KR1019950015174 A KR 1019950015174A KR 19950015174 A KR19950015174 A KR 19950015174A KR 970003457 A KR970003457 A KR 970003457A
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KR
South Korea
Prior art keywords
forming
contact
metal film
diffusion barrier
etching
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KR1019950015174A
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Korean (ko)
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KR100191708B1 (en
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조경수
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김주용
현대전자산업 주식회사
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Priority to KR1019950015174A priority Critical patent/KR100191708B1/en
Publication of KR970003457A publication Critical patent/KR970003457A/en
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Publication of KR100191708B1 publication Critical patent/KR100191708B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 보다 구체적으로는 높이가 상이한 콘택홀의 매립공정을 위한 에치 백 공정시 상기 콘택홀에 의해 형성되는 글로벌 단차 영역에 잔존하는 잔류 금속막을 제거하여 소자의 신뢰성을 확보하는 반도체 소자의 금속 배선 형성방법에 관한 것으로 본 발명은 글로벌 단차를 갖는 반도체 소자의 금속 배선 형성 공정 중, 글로벌 단차부에 잔류하는 금속막을 플라즈마 상태의 아르곤 가스의 식각 특성을 이용하여 제거할 수 있어, 이후, 금속 배선 공정시 브리징 현상을 방지함으로서, 소자의 금속 배선의 신뢰성 증가 및 공정을 단순화하여 소자의 제조 수율을 개선할 수 있다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and more particularly, to remove a residual metal film remaining in a global step area formed by the contact hole during an etch back process for filling a contact hole having a different height. The present invention relates to a method for forming a metal wiring of a semiconductor device to ensure the reliability of the present invention, the metal film remaining in the global step of the semiconductor wiring forming step of the semiconductor device having a global step using the etching characteristics of the argon gas in the plasma state Since it is possible to eliminate the bridging phenomenon during the metal wiring process, it is possible to increase the reliability of the metal wiring of the device and simplify the process to improve the manufacturing yield of the device.

Description

반도체 소자의 금속 배선 형성방법Metal wiring formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도 (가) 내지 (마)는 본 발명에 따른 반도체 소자의 금속 배선 형성을 보인 단면도.2 (a) to (e) are cross-sectional views showing the formation of metal wirings of a semiconductor device according to the present invention.

Claims (5)

하부에 능동 소자 및 수동 소자를 구비한 반도체 기판 상부에 산화막을 형성하고, 높이가 상이한 콘택홀을 형성하는 단계; 상기 전체 구조 상부에 확산 방지막을 형성하는 단계; 상기 확산 방지막 상부에 콘택 매립용 금속막을 상기 콘택홀을 매립할 만큼의 두께로 형성하는 단계; 상기 콘택 매립용 금속막을 플라즈마 상태에서 아르곤 가스로 식각하는 단계; 상기 아르곤 가스의 식각이후 콘택홀 영역을 제외한 확산 방지막 상부에 잔존하는 콘택 매립용 금속막을 아르곤 가스 이외의 식각 가스로 제거하는 단계; 상기 결과물 상부에 금속 배선막과 난반사 방지막을 차례로 형성하는 단계; 및 상기 확산 방지막과 금속 방지막 및 난반사 방지막을 소정의 패턴으로 식각하여 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.Forming an oxide film on an upper portion of the semiconductor substrate having an active element and a passive element, and forming contact holes having different heights; Forming a diffusion barrier over the entire structure; Forming a contact embedding metal film on the diffusion barrier layer to have a thickness sufficient to fill the contact hole; Etching the contact buried metal film with argon gas in a plasma state; Removing the contact embedding metal film remaining on the diffusion barrier layer except for the contact hole region after etching the argon gas with an etching gas other than argon gas; Sequentially forming a metal wiring film and an antireflection film on the resultant product; And forming a metal wiring by etching the diffusion barrier, the metal barrier, and the diffuse reflection barrier in a predetermined pattern. 제1항에 있어서, 상기 콘택 매립용 금속막의 재질은 텅스텐인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The method of claim 1, wherein the contact buried metal film is made of tungsten. 제1항 또는 제2항에 있어서, 상기 콘택 매립용 금속막은 화학 기상 증착법에 의해 형성되는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method of claim 1, wherein the contact buried metal film is formed by a chemical vapor deposition method. 제1항에 있어서, 상기 확산 방지막은 티타늄질화막 또는 내화성 금속막중 선택되는 하나의 막으로 형성되는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method of claim 1, wherein the diffusion barrier layer is formed of one of a titanium nitride layer and a refractory metal layer. 제1항에 있어서, 상기 아르곤 가스의 식각이후 콘택홀 영역을 제외한 확산 방지막 상부에 잔존하는 콘택매립용 금속막을 제거하는 식각 가스로 SF6가스인 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method of claim 1, wherein the etching gas removes the contact buried metal film remaining on the diffusion barrier layer except for the contact hole region after the argon gas is SF 6 gas. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950015174A 1995-06-09 1995-06-09 Forming method for metal wiring in semiconductor device KR100191708B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950015174A KR100191708B1 (en) 1995-06-09 1995-06-09 Forming method for metal wiring in semiconductor device

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Application Number Priority Date Filing Date Title
KR1019950015174A KR100191708B1 (en) 1995-06-09 1995-06-09 Forming method for metal wiring in semiconductor device

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KR100191708B1 KR100191708B1 (en) 1999-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990057826A (en) * 1997-12-30 1999-07-15 김영환 Metal wiring formation method of semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451041B1 (en) * 1997-06-27 2004-12-04 주식회사 하이닉스반도체 Method for forming metal interconnection of semiconductor device to solve problems arising from step between cell area and peripheral circuit area of semiconductor device
KR100480570B1 (en) * 1997-11-13 2005-09-30 삼성전자주식회사 Method for forming tungsten plug for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990057826A (en) * 1997-12-30 1999-07-15 김영환 Metal wiring formation method of semiconductor device

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