KR960026220A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

Info

Publication number
KR960026220A
KR960026220A KR1019940039110A KR19940039110A KR960026220A KR 960026220 A KR960026220 A KR 960026220A KR 1019940039110 A KR1019940039110 A KR 1019940039110A KR 19940039110 A KR19940039110 A KR 19940039110A KR 960026220 A KR960026220 A KR 960026220A
Authority
KR
South Korea
Prior art keywords
semiconductor device
tungsten
manufacturing
barrier metal
plug
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1019940039110A
Other languages
Korean (ko)
Inventor
박상훈
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940039110A priority Critical patent/KR960026220A/en
Publication of KR960026220A publication Critical patent/KR960026220A/en
Ceased legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 장치의 제조방법에 관한 것으로 특히 텅스텐-플러그 형성시 노출되는 장벽 금속(Barrier Metal)의 손실을 보상할 수 있는 반도체 장치의 텅스텐-플러그를 형성하는 반도체 장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device for forming a tungsten-plug of a semiconductor device capable of compensating for the loss of barrier metal exposed during tungsten-plug formation.

반도체 소자가 미세화되고 고집적화됨에 따라, 콘택홀을 매립하는 방법으로 대두된 텅스텐-플러그 기술은 소정의 콘택홀 영역을 구축한 후, 텅스텐을 도포한 다음, 잔류 텅스텐 막을 제거하기 위해 과도식각(over etching)을 실시하면, 텅스텐 막의 손실은 물론이고, 소정부위의 장벽 금속이 제거되어 동공이 발생하여 이후의 알루미늄 합금배선 형성시, 동공(Void) 및 심한 요철 부위로 인하여 반도체 장치의 신뢰성에 악영향을 주게된다.As semiconductor devices become finer and more integrated, the tungsten-plug technology, which has emerged as a method of filling contact holes, establishes a predetermined contact hole area, applies tungsten, and then overetches to remove the remaining tungsten film. ), As well as the loss of the tungsten film, the barrier metal of the predetermined portion is removed to generate pores, which in turn adversely affects the reliability of the semiconductor device due to voids and severe irregularities in forming aluminum alloy wiring. do.

따라서, 본 발명은 텅스텐-플러그의 동공으로 인한 배선 불량을 해결하기 위하여 제2장벽 금속막을 텅스텐플러그 형성 후에 증착함으로써 반도체 장치의 신뢰성을 향상시킬 수 있다.Therefore, the present invention can improve the reliability of the semiconductor device by depositing the second barrier metal film after tungsten plug formation in order to solve the wiring defect due to the hole of the tungsten plug.

Description

반도체 장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도 (가) 내지 (다)는 본 발명의 일 실시예의 제조방법을 설명하기 위한 각 제조공정에 있어서의 반도체 장치의 요부 단면도.2 (a) to 2 (c) are cross-sectional views of principal parts of a semiconductor device in each manufacturing step for explaining the manufacturing method of the embodiment of the present invention.

Claims (3)

반도체 장치의 제조방법에 있어서, 소정의 절연막에 콘택홀을 형성하는 단계; 제1장벽 금속층 및 텅스텐막을 적층하는 단계와; 에치백하는 단계와; 제2장벽 금속층을 적층하는 단계 및 소정의 금속배선을 형성하는 단계로 이루어진 반도체 장치의 제조방법.A method of manufacturing a semiconductor device, comprising: forming a contact hole in a predetermined insulating film; Stacking a first barrier metal layer and a tungsten film; Etching back; A method of manufacturing a semiconductor device, comprising laminating a second barrier metal layer and forming a predetermined metal wiring. 제1항에 있어서 상기 제2장벽 금속층을 적층할 때에, 동일한 식각 챔버내에서 압력 100~300mTorr, 전력 100~1000W, TiCl410~100 SCCM, N210~100 SCCM의 조건으로 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.The method according to claim 1, wherein when the second barrier metal layer is stacked, the second barrier metal layer is formed under the conditions of pressure 100 to 300 mTorr, power 100 to 1000 W, TiCl 4 10 to 100 SCCM, and N 2 10 to 100 SCCM in the same etching chamber. A manufacturing method of a semiconductor device. 제1항에 있어서, 상기 에치백시, 에칭 가스는 SF6, SF6+Ar 또는 SF+O2하인 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein during etching back, the etching gas is under SF 6 , SF 6 + Ar, or SF + O 2 . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940039110A 1994-12-30 1994-12-30 Manufacturing Method of Semiconductor Device Ceased KR960026220A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940039110A KR960026220A (en) 1994-12-30 1994-12-30 Manufacturing Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940039110A KR960026220A (en) 1994-12-30 1994-12-30 Manufacturing Method of Semiconductor Device

Publications (1)

Publication Number Publication Date
KR960026220A true KR960026220A (en) 1996-07-22

Family

ID=66647696

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940039110A Ceased KR960026220A (en) 1994-12-30 1994-12-30 Manufacturing Method of Semiconductor Device

Country Status (1)

Country Link
KR (1) KR960026220A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000017345A (en) * 1998-08-18 2000-03-25 야스카와 히데아키 Method of making semiconductor device
KR100431710B1 (en) * 1996-12-30 2004-08-06 주식회사 하이닉스반도체 Metal wiring formation method of semiconductor device
KR100473161B1 (en) * 1997-12-31 2005-06-22 주식회사 하이닉스반도체 Metal wiring formation method of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100431710B1 (en) * 1996-12-30 2004-08-06 주식회사 하이닉스반도체 Metal wiring formation method of semiconductor device
KR100473161B1 (en) * 1997-12-31 2005-06-22 주식회사 하이닉스반도체 Metal wiring formation method of semiconductor device
KR20000017345A (en) * 1998-08-18 2000-03-25 야스카와 히데아키 Method of making semiconductor device

Similar Documents

Publication Publication Date Title
US20010054765A1 (en) Semiconductor device and method and apparatus for manufacturing the same
KR20000057879A (en) Semiconductor device having interconnection implemented by refractory metal nitride layer and refractory metal silicide layer and process of fabrication thereof
KR960026220A (en) Manufacturing Method of Semiconductor Device
US6831007B2 (en) Method for forming metal line of Al/Cu structure
KR100197669B1 (en) Metal wiring formation method of semiconductor device
KR970052439A (en) Contact hole formation method of semiconductor device
KR100209368B1 (en) Method for forming contact plug of semiconductor device
KR20020096381A (en) Method for forming the contact plug of semiconductor device
JPH0974095A (en) Fabrication of semiconductor device
KR100278274B1 (en) A method for forming stack contact in semiconductor device
JP3301466B2 (en) Method for manufacturing semiconductor device
KR100398033B1 (en) Method for removing key-hole of semiconductor device
KR100607753B1 (en) Metal wiring layer formation method of a semiconductor device
KR100421278B1 (en) Fabricating method for semiconductor device
KR100515373B1 (en) Method for fabricating the via hole for dual damascene interconnection in semiconductor device
KR100318470B1 (en) Metod for fabricating semiconductor device
KR100529440B1 (en) Method for forming a metal line of semiconductor device
KR100236095B1 (en) Interconnecting method of semiconductor device
KR100269662B1 (en) Method for forming conductor plug in semiconductor device
KR970052334A (en) Metal wiring formation method of semiconductor device
KR20060078249A (en) MIM Capacitor Formation Method
KR19980085833A (en) Manufacturing Method of Semiconductor Device
KR20040025110A (en) Method for forming a tungsten plug of semiconductor device
KR960026219A (en) Manufacturing Method of Semiconductor Device
KR970052331A (en) Metal wiring formation method of semiconductor device

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19941230

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19990317

Comment text: Request for Examination of Application

Patent event code: PA02011R01I

Patent event date: 19941230

Comment text: Patent Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20001211

Patent event code: PE09021S01D

E601 Decision to refuse application
PE0601 Decision on rejection of patent

Patent event date: 20010309

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 20001211

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I