KR970002699A - Traffic and load measurement circuit and method of serial communication bus between processors - Google Patents
Traffic and load measurement circuit and method of serial communication bus between processors Download PDFInfo
- Publication number
- KR970002699A KR970002699A KR1019950016169A KR19950016169A KR970002699A KR 970002699 A KR970002699 A KR 970002699A KR 1019950016169 A KR1019950016169 A KR 1019950016169A KR 19950016169 A KR19950016169 A KR 19950016169A KR 970002699 A KR970002699 A KR 970002699A
- Authority
- KR
- South Korea
- Prior art keywords
- address
- flag
- pattern
- traffic
- parallel
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17306—Intercommunication techniques
- G06F15/17318—Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
프로세서간 직렬버스를 통하여 메세지를 교환할 시 직렬버스의 트래픽 및 부하를 측정하는 기술이다.This technology measures the traffic and load of serial buses when exchanging messages through serial buses between processors.
2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention
멀티프로세서를 갖는 시스템에서는 프로세서간 IPC를 수행하는 직렬버스를 통하여 메세지를 교환할 시 직렬버스의 정확한 트래픽이나 로드를 측정할 수 없기 때문에 새로운 기능 및 프로세서 추가시에 오버로드가 걸려 시스템의 성능저하의 원인이 되는 문제를 해결한다.In a multiprocessor system, the exact traffic or load of the serial bus cannot be measured when exchanging messages through a serial bus that performs IPC between processors. Resolve the cause of the problem.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
프로세서간의 직렬버스를 통하여 메세지를 교환중 입력되는 병렬데이타를 미리 설정된 시작플래그 세팅값과 비교하여 시작플래그 패턴을 검출하고, 상기 입력되는 데이타와 미리 설정된 수신어드레스를 비교하여 어드레스 패턴을 검출한 후 데이타 비트수의 카운팅을 시작하여 카운팅중에 상기 입력되는 병렬데이타를 미리 설정된 종료플래그와 비교하여 종료플래그 패턴을 검출하며, 종료플래그 패턴이 검출될 시 카운팅을 종료한 후 상기 카운팅값을 읽어들여 직렬버스의 트래픽 및 부하를 측정한다.The parallel data input during the exchange of messages through the serial bus between the processors is compared with a preset start flag setting value to detect a start flag pattern, and the address pattern is detected by comparing the input data with a preset receive address. The counting of the number of bits is started to compare the input parallel data during counting with the preset end flag to detect the end flag pattern.When the end flag pattern is detected, the end flag pattern is terminated. Measure traffic and load
4. 발명의 중요한 용도4. Important uses of the invention
멀티프로세서를 갖는 시스템에서 프로세서간의 트래픽 및 부하를 측정하는데 적용한다.Applied to measure the traffic and load between processors in a multiprocessor system.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따른 직렬버스의 트래픽 및 과부하 측정회로도.2 is a traffic and overload measurement circuit diagram of a serial bus according to the present invention.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950016169A KR0159659B1 (en) | 1995-06-17 | 1995-06-17 | Serial telecommunication type bus of traffic between processor and load checking circuit and method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950016169A KR0159659B1 (en) | 1995-06-17 | 1995-06-17 | Serial telecommunication type bus of traffic between processor and load checking circuit and method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970002699A true KR970002699A (en) | 1997-01-28 |
KR0159659B1 KR0159659B1 (en) | 1998-12-15 |
Family
ID=19417418
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950016169A KR0159659B1 (en) | 1995-06-17 | 1995-06-17 | Serial telecommunication type bus of traffic between processor and load checking circuit and method thereof |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0159659B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100449695B1 (en) * | 1997-03-20 | 2004-12-03 | 삼성전자주식회사 | Device for controlling bus traffic load on multiprocessor system using shared memory |
-
1995
- 1995-06-17 KR KR1019950016169A patent/KR0159659B1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100449695B1 (en) * | 1997-03-20 | 2004-12-03 | 삼성전자주식회사 | Device for controlling bus traffic load on multiprocessor system using shared memory |
Also Published As
Publication number | Publication date |
---|---|
KR0159659B1 (en) | 1998-12-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR980007258A (en) | I²C communication device using general purpose microcomputer | |
KR970002699A (en) | Traffic and load measurement circuit and method of serial communication bus between processors | |
CN113495225B (en) | Power supply stability test method, system and equipment | |
KR940006014A (en) | Timer circuit with comparator | |
KR930013949A (en) | Information processing device | |
KR0167937B1 (en) | Starting signal discriminating system of data network | |
KR100207926B1 (en) | Pulse width measuring method and its apparatus | |
CN209841904U (en) | Vehicle speed signal detection module | |
US5581561A (en) | Random bit diagnostic for a high resolution measurement system | |
KR0128136Y1 (en) | Board fault detector using no-response of address and access of parallel bus system | |
JPH01286061A (en) | Bus supervising system | |
KR970012165A (en) | Central processing unit signal status monitoring unit | |
KR960017353A (en) | Diagnostic circuit of runaway detection circuit | |
JP3522951B2 (en) | Display device with abnormality detection function | |
JP2513888B2 (en) | Microprocessor | |
JPH06195245A (en) | Monitor timer device | |
KR20060126149A (en) | Apparatus for sensing bus traffic and method for sensing a amount of bus traffic | |
KR970022339A (en) | Sensor monitor device | |
JPS6191797A (en) | Emergency informer | |
JPH055768A (en) | Non-synchronous cpu wait timer circuit for ic tester | |
JPH01278128A (en) | Parity monitor circuit | |
KR910005128A (en) | Malfunction prevention circuit and method of central processing unit | |
JPH10283217A (en) | Device debugging method | |
KR960009479A (en) | Synchronous Source Clock Monitoring Circuit in Digital Exchange | |
KR19980017641A (en) | Interrupt Generator on I2C Bus |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20080704 Year of fee payment: 11 |
|
LAPS | Lapse due to unpaid annual fee |