KR970002699A - Traffic and load measurement circuit and method of serial communication bus between processors - Google Patents

Traffic and load measurement circuit and method of serial communication bus between processors Download PDF

Info

Publication number
KR970002699A
KR970002699A KR1019950016169A KR19950016169A KR970002699A KR 970002699 A KR970002699 A KR 970002699A KR 1019950016169 A KR1019950016169 A KR 1019950016169A KR 19950016169 A KR19950016169 A KR 19950016169A KR 970002699 A KR970002699 A KR 970002699A
Authority
KR
South Korea
Prior art keywords
address
flag
pattern
traffic
parallel
Prior art date
Application number
KR1019950016169A
Other languages
Korean (ko)
Other versions
KR0159659B1 (en
Inventor
권재광
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950016169A priority Critical patent/KR0159659B1/en
Publication of KR970002699A publication Critical patent/KR970002699A/en
Application granted granted Critical
Publication of KR0159659B1 publication Critical patent/KR0159659B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
    • G06F15/17318—Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

프로세서간 직렬버스를 통하여 메세지를 교환할 시 직렬버스의 트래픽 및 부하를 측정하는 기술이다.This technology measures the traffic and load of serial buses when exchanging messages through serial buses between processors.

2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention

멀티프로세서를 갖는 시스템에서는 프로세서간 IPC를 수행하는 직렬버스를 통하여 메세지를 교환할 시 직렬버스의 정확한 트래픽이나 로드를 측정할 수 없기 때문에 새로운 기능 및 프로세서 추가시에 오버로드가 걸려 시스템의 성능저하의 원인이 되는 문제를 해결한다.In a multiprocessor system, the exact traffic or load of the serial bus cannot be measured when exchanging messages through a serial bus that performs IPC between processors. Resolve the cause of the problem.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

프로세서간의 직렬버스를 통하여 메세지를 교환중 입력되는 병렬데이타를 미리 설정된 시작플래그 세팅값과 비교하여 시작플래그 패턴을 검출하고, 상기 입력되는 데이타와 미리 설정된 수신어드레스를 비교하여 어드레스 패턴을 검출한 후 데이타 비트수의 카운팅을 시작하여 카운팅중에 상기 입력되는 병렬데이타를 미리 설정된 종료플래그와 비교하여 종료플래그 패턴을 검출하며, 종료플래그 패턴이 검출될 시 카운팅을 종료한 후 상기 카운팅값을 읽어들여 직렬버스의 트래픽 및 부하를 측정한다.The parallel data input during the exchange of messages through the serial bus between the processors is compared with a preset start flag setting value to detect a start flag pattern, and the address pattern is detected by comparing the input data with a preset receive address. The counting of the number of bits is started to compare the input parallel data during counting with the preset end flag to detect the end flag pattern.When the end flag pattern is detected, the end flag pattern is terminated. Measure traffic and load

4. 발명의 중요한 용도4. Important uses of the invention

멀티프로세서를 갖는 시스템에서 프로세서간의 트래픽 및 부하를 측정하는데 적용한다.Applied to measure the traffic and load between processors in a multiprocessor system.

Description

프로세서간 직렬통신방식버스의 트래픽 및 부하 측정회로 및 방법Traffic and load measurement circuit and method of serial communication bus between processors

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 직렬버스의 트래픽 및 과부하 측정회로도.2 is a traffic and overload measurement circuit diagram of a serial bus according to the present invention.

Claims (2)

멀티프로세서를 갖는 시스템에서 프로세서간 직렬통신방식버스의 트래픽 및 부하 측정회로에 있어서, 각 프로세서간의 직렬통신을 수행할 수 있도록 제어 처리하며, 외부입출력장치와 MMC를 통해 설정된 시작플래그와 종료플래그에 대한 데이타 및 수신어드레스를 발생하고, 측정된 트래픽 및 과부하 측정값을 입력하여 표시하는 콘트롤 및 모니터부(22)와, 버스를 통해 입력된 클럭신호(CLK), 데이타(DATA), 제어신호(CONTROL)를 입력하여 병렬신호로 변환하는 병직렬변환부(10)와, 상기 콘트롤 및 모니터부(22)로부터 발생된 시작플래그와 종료플래그를 받아 저장하는 플래그 세팅부(14)와, 상기 직병렬변환부(10)로부터 병렬로 변환된 시작플래그신호 또는 종료플래그를 상기 플래그 세팅부(14)로부터 출력된 시작플래그 세팅값 또는 종료플래그 세팅값을 비교하여 플래그 패턴을 검출하는 플래그 패턴검출부(12)와, 상기 콘트롤 및 모니터부(22)로부터 발생된 수신어드레스를 받아 저장하는 어드레스 세팅부(18)와, 상기 플래그 패턴검출부(12)로부터 시작패턴 검출신호를 받아 상기 직병렬변환부(10)로부터 병렬로 변환된 어드레스를 상기 어드레스 세팅부(18)로부터 출력된 어드레스와 비교하여 어드레스 패턴을 검출하여 카운팅 시작신호를 발생하는 어드레스 패턴검출부(16)와, 상기 어드레스 패턴검출부(16)으로부터 카운팅 시작신호를 입력하여 데이타 비트를 카운팅하여 출력하는 카운터(20)로 구성으로 구성함을 특징으로 하는 회로.In the traffic and load measurement circuit of the inter-processor serial communication bus in a multi-processor system, a control process is performed to perform serial communication between the processors, and the start and end flags set through the external I / O device and the MMC A control and monitor unit 22 which generates data and a reception address and inputs and displays measured traffic and overload measurement values, and a clock signal CLK, data DATA, and control signal inputted through a bus. A parallel and serial converter 10 for converting a parallel signal into a parallel signal, a flag setting unit 14 for receiving and storing a start flag and an end flag generated from the control and monitor unit 22, and the serial and parallel converter. Compare the start flag setting value or the end flag setting value outputted from the flag setting section 14 with the start flag signal or the end flag converted in parallel from (10). A flag pattern detection unit 12 for detecting a flag pattern, an address setting unit 18 for receiving and storing a reception address generated from the control and monitor unit 22, and a start pattern detection from the flag pattern detection unit 12 An address pattern detection unit 16 which detects an address pattern and generates a counting start signal by comparing an address converted in parallel from the serial-to-parallel conversion unit 10 with an address received from the address setting unit 18; And a counter (20) for inputting a counting start signal from the address pattern detector (16) to count and output data bits. 멀티프로세서를 갖는 시스템에서 프로세서간 직렬통신방식버스의 트래픽 및 부하 측정회로에 있어서, 프로세서간에 직렬버스를 통하여 메세지를 교환중 입력되는 병렬데이타를 미리 설정된 시작플래그 세팅값과 비교하여 시작플래그 패턴을 검출하는 과정과, 상기 시작플래그가 검출될 시 상기 입력되는 데이타와 미리 설정된 수신어드레스를 비교하여 어드레스 패턴을 검출하는 과정과, 상기 어드레스 패턴이 검출될 시 데이타 비트수의 카운팅을 시작하는 과정과, 상기 카운팅중에 상기 입력되는 병렬데이타를 종료플래그와 비교하여 종료플래그 패턴을 검출하는 과정과, 상기 종료플래그가 검출될 시 카운팅을 종료하는 과정과, 상기 카운팅이 종료될 시 상기 카운팅값을 읽어들여 직렬버스의 트래픽 및 부하를 측정하는 과정으로 이루어짐을 특징으로 하는 방법.In the traffic and load measurement circuit of the inter-processor serial communication bus in a multiprocessor system, the start flag pattern is detected by comparing the parallel data input during exchanging messages through the serial bus between the processors with a preset start flag setting value. And detecting an address pattern by comparing the input data with a predetermined reception address when the start flag is detected, starting counting the number of data bits when the address pattern is detected, and A process of detecting an end flag pattern by comparing the input parallel data with an end flag during counting, an end of counting when the end flag is detected, and reading the count value when the counting ends To measure traffic and load How to. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950016169A 1995-06-17 1995-06-17 Serial telecommunication type bus of traffic between processor and load checking circuit and method thereof KR0159659B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950016169A KR0159659B1 (en) 1995-06-17 1995-06-17 Serial telecommunication type bus of traffic between processor and load checking circuit and method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950016169A KR0159659B1 (en) 1995-06-17 1995-06-17 Serial telecommunication type bus of traffic between processor and load checking circuit and method thereof

Publications (2)

Publication Number Publication Date
KR970002699A true KR970002699A (en) 1997-01-28
KR0159659B1 KR0159659B1 (en) 1998-12-15

Family

ID=19417418

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950016169A KR0159659B1 (en) 1995-06-17 1995-06-17 Serial telecommunication type bus of traffic between processor and load checking circuit and method thereof

Country Status (1)

Country Link
KR (1) KR0159659B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100449695B1 (en) * 1997-03-20 2004-12-03 삼성전자주식회사 Device for controlling bus traffic load on multiprocessor system using shared memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100449695B1 (en) * 1997-03-20 2004-12-03 삼성전자주식회사 Device for controlling bus traffic load on multiprocessor system using shared memory

Also Published As

Publication number Publication date
KR0159659B1 (en) 1998-12-15

Similar Documents

Publication Publication Date Title
KR980007258A (en) I²C communication device using general purpose microcomputer
KR970002699A (en) Traffic and load measurement circuit and method of serial communication bus between processors
CN113495225B (en) Power supply stability test method, system and equipment
KR940006014A (en) Timer circuit with comparator
KR930013949A (en) Information processing device
KR0167937B1 (en) Starting signal discriminating system of data network
KR100207926B1 (en) Pulse width measuring method and its apparatus
CN209841904U (en) Vehicle speed signal detection module
US5581561A (en) Random bit diagnostic for a high resolution measurement system
KR0128136Y1 (en) Board fault detector using no-response of address and access of parallel bus system
JPH01286061A (en) Bus supervising system
KR970012165A (en) Central processing unit signal status monitoring unit
KR960017353A (en) Diagnostic circuit of runaway detection circuit
JP3522951B2 (en) Display device with abnormality detection function
JP2513888B2 (en) Microprocessor
JPH06195245A (en) Monitor timer device
KR20060126149A (en) Apparatus for sensing bus traffic and method for sensing a amount of bus traffic
KR970022339A (en) Sensor monitor device
JPS6191797A (en) Emergency informer
JPH055768A (en) Non-synchronous cpu wait timer circuit for ic tester
JPH01278128A (en) Parity monitor circuit
KR910005128A (en) Malfunction prevention circuit and method of central processing unit
JPH10283217A (en) Device debugging method
KR960009479A (en) Synchronous Source Clock Monitoring Circuit in Digital Exchange
KR19980017641A (en) Interrupt Generator on I2C Bus

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080704

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee