KR970002596A - 클럭 위상을 이용한 캐리증가 가산기 - Google Patents

클럭 위상을 이용한 캐리증가 가산기 Download PDF

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Publication number
KR970002596A
KR970002596A KR1019950017888A KR19950017888A KR970002596A KR 970002596 A KR970002596 A KR 970002596A KR 1019950017888 A KR1019950017888 A KR 1019950017888A KR 19950017888 A KR19950017888 A KR 19950017888A KR 970002596 A KR970002596 A KR 970002596A
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South Korea
Prior art keywords
partial
signal
adder
carry
module
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KR1019950017888A
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English (en)
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KR100197354B1 (ko
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장현식
박동석
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김주용
현대전자산업 주식회사
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Priority to KR1019950017888A priority Critical patent/KR100197354B1/ko
Priority to US08/668,363 priority patent/US5912833A/en
Priority to TW085107800A priority patent/TW425526B/zh
Publication of KR970002596A publication Critical patent/KR970002596A/ko
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Publication of KR100197354B1 publication Critical patent/KR100197354B1/ko

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

본 발명은 속도가 빠르면서도, 일반 빠른 가산기 구조들보다 훨씬 적은 면적만을 필요로 하는 클럭 위상을 이용한 캐리증가 가산기(CIA)에 관한 것으로, 가산할 두 입력(a,b)데이타의 소정 비트를 하나의 모듈로 하여 부분합과 부분 캐리값을 발생하는 N(1,2,…N)개의 부분 가산기 모듈(RCA)을 포함하는 CIA에 있어서, 조건적 증가(Conditional Increment)부분을 가산기 모듈인 RCA를 통해 중복 계산하도록 하여 여타의 고속용 가산기들에 비해, 무척 적은 양의 면적에서 실현가능하고, 이러한 속도와 면적의 잇점은 가산 비트 폭(addition bit width)이 클수록 커지는 효과가 있다.

Description

클럭 위상을 이용한 캐리증가 가산기
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 따른 8비트 CIA의 구성 블럭도, 제3도는 본 발명에 따른 16 비트 CIA의 구성 블럭도.

Claims (4)

  1. 가산할 두 입력(a,b)데이타의 소정 비트를 하나의 모듈로 하여 부분합과 부분 캐리값을 발생하는 N(1,2,…N)개의 부분 가산기 모듈을 포함하는 캐리증가 가산기(CIA)에 있어서, 부분 입력을 가사한 합과 최하위 캐리를 발생하는 최하위 부분 가산기 모듈과, 부분 입력을 가산하여 각각 캐리와 부분합을 출력하되, 부분 가산기 모듈중 최하위 부분 가산기 모듈을 제외한 N-1개의 상위 부분 가산기 모듈과, 상기 상위 부분 가산기 모듈의 부분합이 모두 '1'인지를 판별하여 부분 가산결과 검출신호를 출력하는 N-1개의 부분 가산결과 검출수단과, 상기 최하위 부분 가산기 모듈의 캐리와 N-1개의 상위 부분 가산기 모듈 각각에서 출력되는 캐리와 상기 부분 가산결과 검출신호를 입력받아 증가신호를 출력하는 증가신호 발생수단과, 외부로부터 입력되는 클럭신호와 상기 증가신호를 입력으로 하여 상기 상위 부분 가산기 모듈이 상기 클럭신호의 제1특정 위상에 따라 부분 입력을 합산하여 발생되는 캐리값을 출력하거나 상위 클럭신호의 제2특정 위상에 따라 입력되는 증가신호를 상기 부분 입력을 합산한 값에 가산하여 최종 출력값을 출력하도록 하는 N-1개의 제어수단을 구비하는 것을 특징으로 하는 클럭위상을 이용한 CIA.
  2. 제1항에 있어서, 상기 부분 가산결과 검출수단은, 두 입력의 소정비트를 배타적 논리합 하는 다수의 배타적 논리합 게이타와, 상기 다수의 배타적 논리합 게이트의 출력을 논리곱하는 논리곱 게이트를 구비하는 것을 특징으로 하는 클럭위상을 이용한 CIA.
  3. 제1항에 있어서, 상기 증가신호 발생수단은, N은 자연수, INC은 증가신호, PC는 캐리값, PSN은 판별값을 각각 나타낼 때, INC(N)=PC(N-1)+(PSN(N-1)·PC(N-2))+…+(PSN(N-1)·PSN(N-2)…PC0)에 의해 구성되는 것을 특징으로 하는 클럭위상을 이용한 CIA.
  4. 제1항에 있어서, 상기 제어수단은, 상기 증가신호 블생수단으로부터 출력되는 증가신호를 반전시키는 인버터어와, 외부로부터 입력되는 클럭신호와 상기 인버어터의 출력신호를 부정 논리합 하는 부정 논리합 게이트를 구비하는 것을 특징으로 하는 클럭위상을 이용한 CIA.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950017888A 1995-06-28 1995-06-28 클럭 위상을 이용한 캐리증가 가산기 KR100197354B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950017888A KR100197354B1 (ko) 1995-06-28 1995-06-28 클럭 위상을 이용한 캐리증가 가산기
US08/668,363 US5912833A (en) 1995-06-28 1996-06-26 Carry increment adder using clock phase
TW085107800A TW425526B (en) 1995-06-28 1996-06-28 Carry increment adder using clock phase

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950017888A KR100197354B1 (ko) 1995-06-28 1995-06-28 클럭 위상을 이용한 캐리증가 가산기

Publications (2)

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KR970002596A true KR970002596A (ko) 1997-01-28
KR100197354B1 KR100197354B1 (ko) 1999-06-15

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US (1) US5912833A (ko)
KR (1) KR100197354B1 (ko)
TW (1) TW425526B (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480446B1 (ko) * 1997-09-26 2005-06-20 로께뜨프레르 특정형태의말티톨결정,이를함유하는결정성조성물및이들의제조방법

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11143685A (ja) * 1997-06-24 1999-05-28 Internatl Business Mach Corp <Ibm> キャリー・スキップ・アダー
US6735612B1 (en) 1997-06-24 2004-05-11 International Business Machines Corporation Carry skip adder
US6832235B1 (en) * 2001-02-16 2004-12-14 Texas Instruments Incorporated Multiple block adder using carry increment adder
US7007059B1 (en) * 2001-07-30 2006-02-28 Cypress Semiconductor Corporation Fast pipelined adder/subtractor using increment/decrement function with reduced register utilization
US7058678B2 (en) * 2002-01-02 2006-06-06 International Business Machines Corporation Fast forwarding ALU
DE10215785A1 (de) * 2002-04-10 2003-10-30 Infineon Technologies Ag Rechenwerk und Verfahren zum Addieren
US11385864B2 (en) * 2019-07-02 2022-07-12 Facebook Technologies, Llc Counter based multiply-and-accumulate circuit for neural network

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3069310D1 (en) * 1980-11-03 1984-10-31 Itt Ind Gmbh Deutsche Binary mos ripple carry parallel adder/subtractor and appropriate adding/subtracting stage
JPS6149233A (ja) * 1984-08-17 1986-03-11 Nec Corp 高速デジタル加減算回路
FR2628232B1 (fr) * 1988-03-07 1994-04-08 Etat Francais Cnet Additionneur de type recursif pour calculer la somme de deux operandes
US5097436A (en) * 1990-01-09 1992-03-17 Digital Equipment Corporation High performance adder using carry predictions
KR920006321B1 (ko) * 1990-04-19 1992-08-03 정호선 신경회로망을 이용한 부동소수점방식 곱셈기회로
US5257218A (en) * 1992-01-06 1993-10-26 Intel Corporation Parallel carry and carry propagation generator apparatus for use with carry-look-ahead adders
JPH05233219A (ja) * 1992-02-18 1993-09-10 Nec Ic Microcomput Syst Ltd 半導体集積回路のキャリー先取り回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480446B1 (ko) * 1997-09-26 2005-06-20 로께뜨프레르 특정형태의말티톨결정,이를함유하는결정성조성물및이들의제조방법

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US5912833A (en) 1999-06-15
KR100197354B1 (ko) 1999-06-15
TW425526B (en) 2001-03-11

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