KR960038992A - Bit line selection circuit - Google Patents

Bit line selection circuit Download PDF

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Publication number
KR960038992A
KR960038992A KR1019950010122A KR19950010122A KR960038992A KR 960038992 A KR960038992 A KR 960038992A KR 1019950010122 A KR1019950010122 A KR 1019950010122A KR 19950010122 A KR19950010122 A KR 19950010122A KR 960038992 A KR960038992 A KR 960038992A
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KR
South Korea
Prior art keywords
bit line
line selection
selection signal
charging
level
Prior art date
Application number
KR1019950010122A
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Korean (ko)
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KR0152956B1 (en
Inventor
장성진
Original Assignee
문정환
엘지반도체 주식회사
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Publication date
Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR1019950010122A priority Critical patent/KR0152956B1/en
Priority to US08/637,917 priority patent/US5781487A/en
Priority to JP8109889A priority patent/JP2881722B2/en
Publication of KR960038992A publication Critical patent/KR960038992A/en
Application granted granted Critical
Publication of KR0152956B1 publication Critical patent/KR0152956B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Electronic Switches (AREA)

Abstract

본 발명의 비트라인 선택회로는, 로우 어드레스 선택신호가 디스에이블이면 비트라인 선택신호를 전원레벨로 유지시키고, 상기 로우 어드레스 선택신호가 인에이블되면 선택된 비트라인 선택신호는 승압레벨로 하고, 선택되지 않는 비트라인 선택신호는 접지레벨로 하기 위한 비트라인 선택부와, 선택된 비트라인 신호가 상기 로우 어드레스 선택신호의 디스에이블됨에 따라 승압레벨에서 전원레벨로 방전될 때 나오는 전하를 소정값 충전하여 재활용하기 위한 전하 충전부를 포함하여 구성되며, 선택된 비트라인 선택신호가 로우 어드레스 선택신호의 디스에이블됨에 따라 Vpp에서 전원전압으로 프리자치될 때 이를 저장하기 위한 전하충전부를 연결하여, 전원전압으로 흘러보내는 Vpp전하중 일부를 재활용하므로써 Vpp전하량의 소모를 50% 이상 감소시킬 수 있는 효과가 있다.The bit line selection circuit of the present invention maintains the bit line selection signal at the power supply level when the row address selection signal is disabled, and selects the selected bit line selection signal as the boost level when the row address selection signal is enabled. Bit line selection signal for the non-bit line selection signal to the ground level, and by charging a predetermined value for the charge generated when the selected bit line signal is discharged from the boost level to the power level as the row address selection signal is disabled And a charge charger for storing the selected bit line selection signal when the selected bit line selection signal is pre- superposed to the power supply voltage as the row address selection signal is disabled. pp By recycling a portion of the charge V pp consumption of the charge at least 50% It is capable of little effect.

Description

비트라인 선택회로Bit line selection circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도는 본 발명에 의한 비트라인 센스 증폭부 어레이와 셀 어레이 및 비트라인 선택부의 연결구성 블록도, 제6도는 본 발명에 의한 비트라인 선택회로도.5 is a block diagram illustrating a connection structure of a bit line sense amplifier unit array, a cell array, and a bit line selection unit according to the present invention, and FIG. 6 is a bit line selection circuit diagram according to the present invention.

Claims (5)

로우 어드레스 선택회로가 디스에이블이면 비트라인 선택신호를 전원레벨로 유지시키고, 상기 로우 어드레스 선택신호가 인에이블되면 선택된 비트라인 선택신호는 승압레벨로 하고, 선택되지 않는 비트라인 선택신호는 접지레벨로 하기 위한 비트라인 선택부와, 선택된 비트라인 신호가 상기 로우 어드레스 선택신호의 디스에이블됨에 따라 승압레벨에서 전원레벨로 방전될 때 나오는 전하를 소정값 충전하여 재활용하기 위한 전하 충전부를 포함하여 구성된 것을 특징으로 하는 비트라인 선택회로.If the row address selection circuit is disabled, the bit line selection signal is maintained at a power supply level. If the row address selection signal is enabled, the selected bit line selection signal is at a boost level, and the unselected bit line selection signal is at a ground level. And a charge charging unit for charging and recycling a predetermined value of charges generated when the selected bit line signal is discharged from the boost level to the power level as the selected bit line signal is disabled. Bit line selection circuit. 제1항에 있어서, 상기 비트라인 선택부는 각각이 비트라인 선택신호에 대해 전원전압과 연결된 제1트랜지스터와, 승압전압과 연결된 제2트랜지스터와, 상기 제1트랜지스터와 제2트랜지스터의 턴온, 턴오프를 제어하여 두 트랜지스터 사이의 커런트 경로의 오동작을 방지하기 위한 지연기를 포함하여 구성된 것을 특징으로 하는 비트라인 선택회로.2. The bit line selector of claim 1, wherein the bit line selector comprises a first transistor connected to a power supply voltage, a second transistor connected to a boosted voltage, a turn-on and turn-off of the first transistor and the second transistor, respectively. And a delayer configured to control an operation to prevent a malfunction of the current path between the two transistors. 제1항에 있어서, 상기 충전부는 충전을 위한 충전용 트랜지스터와, 충전량을 펌핑하기 위한 인버터부와, 전하 충전에 의한 재활용시 충전레벨이 전원레벨 이하로 방전되는 것을 방지하기 위한 엔모스 트랜지스터를 포함하여 구성된 것을 특징으로 하는 비트라인 선택회로.The charging unit of claim 1, wherein the charging unit includes a charging transistor for charging, an inverter unit for pumping a charging amount, and an NMOS transistor for preventing a charge level from being discharged below a power level during recycling by charge charging. And a bit line selection circuit. 제1항에 있어서, 상기 전하 충전부는 복수개의 비트라인 선택부와 공유하는 것을 특징으로 하는 비트라인 선택회로.The bit line selection circuit of claim 1, wherein the charge charger is shared with a plurality of bit line selectors. 제2항에 있어서, 상기 인버터부는 스윙폭이 일정값으로 제한되는 것을 특징으로 하는 비트라인 선택회로.The bit line selection circuit of claim 2, wherein the inverter unit has a swing width limited to a predetermined value. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950010122A 1995-04-27 1995-04-27 The selecting circuit of bit line KR0152956B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950010122A KR0152956B1 (en) 1995-04-27 1995-04-27 The selecting circuit of bit line
US08/637,917 US5781487A (en) 1995-04-27 1996-04-26 Bit line selection circuit
JP8109889A JP2881722B2 (en) 1995-04-27 1996-04-30 Bit line selection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950010122A KR0152956B1 (en) 1995-04-27 1995-04-27 The selecting circuit of bit line

Publications (2)

Publication Number Publication Date
KR960038992A true KR960038992A (en) 1996-11-21
KR0152956B1 KR0152956B1 (en) 1998-12-01

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KR1019950010122A KR0152956B1 (en) 1995-04-27 1995-04-27 The selecting circuit of bit line

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100351054B1 (en) * 2000-06-13 2002-09-05 삼성전자 주식회사 Semiconductor memory device having boosted voltage stabilization circuit
KR100516695B1 (en) * 1999-12-30 2005-09-22 주식회사 하이닉스반도체 Row active method of semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100516695B1 (en) * 1999-12-30 2005-09-22 주식회사 하이닉스반도체 Row active method of semiconductor memory device
KR100351054B1 (en) * 2000-06-13 2002-09-05 삼성전자 주식회사 Semiconductor memory device having boosted voltage stabilization circuit

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Publication number Publication date
KR0152956B1 (en) 1998-12-01

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