KR0152956B1 - The selecting circuit of bit line - Google Patents

Abstract

The bit line selection circuit of the present invention maintains the bit line selection signal at the power supply level when the row address selection signal is disabled, and selects the selected bit line selection signal as the boost level when the row address selection signal is enabled. The bit line selection signal, which is not used, is a bit line selection unit for setting a ground level, and a charge for recharging and recharging a charge generated when the selected bit line signal is discharged from the boost level to the power level as the row address selection signal is disabled. It includes a charge charging unit, and part of the Vpp charge flowing to the power supply voltage by connecting a charge charger for storing when the selected bit line selection signal is precharged from Vpp to the power supply voltage as the row address selection signal is disabled. Reduces Vpp Charge by More Than 50% by Recycling There are effects that can kill.

Description

Bit line selection circuit

1 is a configuration diagram of a bit line and a bit line sense amplifier according to the related art.

2 is a bit line selection circuit diagram according to the prior art.

3 is a block diagram illustrating a connection structure of a bit line sense amplifier array, a cell array, and a bit line selector according to the related art.

4 is an operation timing diagram of each component of the bit line selection circuit according to the prior art.

5 is a block diagram illustrating a connection structure of a bit line sense amplifier array, a cell array, and a bit line selector according to the present invention.

6 is a bit line selection circuit diagram according to the present invention.

7 is an operation timing diagram of each component of the bit line selection circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

20: bit line sense amplifier array 25: cell array

30: bit line selection unit 40: charge charging unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a bit line selection circuit for reducing power consumption due to an internal boost voltage (Vpp) when selecting a bit line in a DRAM.

In general, DRAMs are divided into two blocks of bit lines BL, as shown in FIG. ) Share one bit line sense amplifier (BLSA), there is a need to ensure that only the bit line pair sharing the one bit line sense amplifier (BLSA) becomes the input of the bit line sense amplifier. .

To this end, a commonly used nMOS transistor is an nMOS transistor, which is placed at both ends of the bit line sense amplifier to turn on or turn off a specific bit line. do.

Here, a circuit for generating a control signal for turning the transistor on or off is a bit line selection circuit, and when the transistor is turned on, a gate bias is sufficient so that the data in the cell is sufficient for the bit line sense. In order to be delivered to the amplifier, it is generally equal to the voltage applied at the word line enable, and this voltage is a specific voltage generated internally higher than the internal power supply voltage (Vcc), that is, the boost voltage (Vpp). ).

2 illustrates a conventional bit line selection circuit, which includes a NAND gate NAND1 for logical combination of input signals B and C, and a delayer 1 for delaying an output of the NAND gate. And inverters sequentially connected between a NOR gate NOR1 for logically combining the output of the NAND gate and a delayed value of the NAND gate, an application terminal of the input signal B, and a gate terminal of the PMOS MP2. The inverters INV5 and INV6 sequentially connected between INV1 to INV3, the input terminal of the input signal C, and the gate terminal of the NMOS MN4, and the output D of the inverter INV6 are inverted again. Inverter INV4, PMOS MP1 using the output G of the inverter INV4 as a gate input, and NMOS MN1 using the output F of the inverter INV2 as a gate input. MN3 and NMOS MN2 whose gate output is the output E of the NOR gate NOR1. And a PMOS (MP2) having the output (L) of the inverter (INV3) as an input. The operation thereof will be described with reference to FIGS. 3 and 4 as follows.

First, the row address selection signal of FIG. Is enabled, one specific block of a plurality of blocks including the bit line sense amplifier array 20, the cell array 25, and the bit line selector 10 in FIG. Is selected.

The bit line selector then operates to select a particular bit line to read or write data to the bit line allocated thereto.

That is, the signals of (j) and (k) are maintained at the internal power supply voltage (Vcc) to prevent noise on the bit line until the row address selection signal of the (a) is enabled. The NMOS gate signal I is boosted to Vpp to transfer the data of the cell to the BLSA, and the NMOS gate signal H of the unselected block goes to ground (Vss) to turn off the transistor, and all operations are performed. At the end, the row address selection signal is disabled.

That is, in the case of using the conventional bit line selection circuit as described above, when the bit line is selected for a specific block, the NMOS gate signals H and I have many load components such as resistance and capacitance, so that the voltage of the boosted voltage (Vpp) of the entire DRAM is increased. The large Vpp power, which accounts for more than 40% of the consumption, is used, and the transistor connected to the power supply voltage must be turned off first, and the transistor connected to Vpp must be turned on, but if this is misaligned, the current path is shortened from the Vpp to the supply voltage. There is a problem in that the Vpp power is wasted.

Accordingly, an object of the present invention is to provide a power supply voltage by connecting a charge charger for storing the selected bit line selection signal when it is precharged to a power supply voltage at Vpp as the row address selection signal is disabled. By recycling some of the Vpp charge that flows into the circuit, it provides a bit line selection circuit that can reduce power consumption.

In order to achieve the above object, the bit line selection circuit of the present invention maintains the bit line selection signal at a power supply level when the row address selection signal is disabled, and the selected bit line selection signal is boosted when the row address selection signal is enabled. The bit line selection signal is set to a level and the unselected bit line selection signal is set to a ground level, and the charges generated when the selected bit line signal is discharged from the boost level to the power supply level are disabled as the row address selection signal is disabled. Characterized in that it comprises a charge charging unit for recycling by charging the value.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

In the bit line selection circuit of the present invention, as shown in FIG. 5, the charge charging unit 40 for recycling the charge of Vpp is connected to be shared by several bit line selection units 30. Accordingly, by adding a pumping circuit to the charge charging unit 40, more Vpp charge can be recycled.

As shown in FIG. 6, the bit line selector 30 boosts the first transistors M2 and M6 connected to the power supply voltage VCC for the respective bit line select signals H and I. The second transistors M3 and M7 connected to the voltage VPP and the delay 31 for controlling the turn-on and turn-off of the first transistor and the second transistor to prevent malfunction of the current path between the two transistors are provided. The charge charging unit 40 includes a charging NMOS transistor M14 for charging, and an inverter unit 41 for pumping the charging amount by attaching an appropriate number of NMOS diodes to the ground level to reduce the swing width. ) And an NMOS transistor M19 for preventing the charge level from being discharged below the power supply level during recycling by charge charging. Referring to FIG. 7, the operation will be described below.

The signal G of (b) is a row address selection signal of (a). If the signal C in (d) is enabled before Vpp is enabled, the inverter operates with an appropriate number of NMOS diodes in the ground to reduce the swing width, thereby transferring the potential of the charge storage capacitor. Increase the swing width compared to the potential.

That is, if node R and node H have the same capacitance, node R has a precharge level of 5 / 4Vcc and a swing width of 1 / 2Vcc, then the voltage of node R becomes 7 / 4Vcc. When enabled, a delayed signal E of a predetermined time and a signal K of the (f) degree, which is the logical product of the signal C, are given to the gate inputs of the NMOS transistors M3 and M7 having Vcc as the source bits of (o) and (q) degrees. The line select signals H and I are plotted.

Then, the signal N in (i) is enabled at Vpp with the pulse width as delayed to turn on the NMOS M8. At this time, the charge pre-charged in the NMOS M14 is moved to change the voltage of the bit line selection signal H. Rising above Vcc, if the capacitance of NMOS MN14 is equal to the loading capacitance of bitline select signal H, the signal H level should be (7 / 4Vcc + Vcc) / 2 = 11 / 8Vcc by charge division. Assuming that Vtn = 1 / 4Vcc and Vpp = 3 / 2Vcc, the amount of charge transferred from node R to node H is limited until the voltage of node H becomes 5 / 4Vcc.

Therefore, after the charge distribution is completed, the node R becomes 7 / 4Vcc and the node H becomes 5 / 4Vcc, which is half of the required Vpp charge amount supplied from the capacitor, and then C, (d) and (e) degrees, The signal (M) in (h) of the E signal is summed to the gate input of PMOS (M2) having Vpp as a source with a predetermined delay interval from the signal K in (f), thereby raising the bit line selection signal H to Vpp. Let's do it.

In addition, the bit line selection signal I adjacent to the BLSA receives the signal L at the (g) degree during the delay, and the NMOS M5 is turned on to become Vss, thereby disconnecting the BLSA, which is sooner than when H goes to Vpp. The reason is that the bit line selection signals H and I have a long loading time, so the connection time with the unused bit line is quickly disconnected to give the word line time to enable.

If you do not need this time, you can use the inverted signal of the signal to set the signal I to Vss.After all the operations are complete, the signal G is disabled before the signal C is disabled after the row address select signal is disabled. To lower the voltage at node R to Vcc. After that, when signal C is disabled, signal M is disabled to Vpp, which disconnects signal H to Vpp; when signal N is enabled by a pulse, the capacitance of NMOS MN8 and the capacitance of signal H at the bit line selector are charged. Nodes R and H become (Vcc + 3 / 2Vcc) / 2 = 5 / 4Vcc.

The reason for using the pumping principle is to increase the Vpp recycling charge, and the reason for reducing the swing width of the inverter is to avoid using Vcc's power more than necessary when pumping.

After signal N is disabled, signal K precharges signal H to Vcc, and signal I is precharged to Vcc by signal K after plotting by signal L, where signals D and Q are fixed to Vpp. The signals O and P are fixed at Vss. If the signal D is enabled, the operations of the signals H and I are changed.

In addition, when the chip is operated for the first time, when the chip is operated, the node R is floated, and thus the NMOS transistor M9 becomes less than Vcc at the time of charge distribution for charge recycling. This transistor was added to prevent this, and the signal F precharges the node R to Vcc at chip power-up so that there is at least no charge loss during the first cycle.

As described above, according to the present invention, when the selected bit line selection signal is precharged from the Vpp to the power supply voltage as the row address selection signal is disabled, it connects a charge charger for storing the Vpp charge to be sent to the power supply voltage. By recycling a part, the consumption of Vpp charge can be reduced by more than 50%.

Claims (5)

When the row address selection signal is disabled, the bit line selection signal is maintained at the power supply level. When the row address selection signal is enabled, the selected bit line selection signal is at the boost level, and the unselected bit line selection signal is at the ground level. And a charge charging unit for charging and recycling a predetermined value of charges generated when the selected bit line signal is discharged from the boost level to the power level as the selected bit line signal is disabled. Bit line selection circuit. The bit line selector of claim 1, wherein the bit line selector comprises: a first transistor connected to a power supply voltage, a second transistor connected to a boosted voltage, a turn-on and turn-off of the first transistor and the second transistor; And a delayer configured to control an operation to prevent a malfunction of the current path between the two transistors. The method of claim 1, wherein the charge charging unit is a charge transistor for charging, an inverter unit for pumping the charge amount, and the NMOS transistor for preventing the charge level is discharged below the power supply level during recycling by charge charging Bit line selection circuit comprising a. The bit line selection circuit of claim 1, wherein the charge charger is shared with a plurality of bit line selectors. The bit line selection circuit of claim 2, wherein the inverter unit has a swing width limited to a predetermined value.