JP3243249B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Industrial applications]

The present invention relates to a semiconductor memory device using a word line boosting method suitable for a large capacity memory.

[Prior art]

Generally, DRAM (Dynamic Random Access
Memory), in order to improve noise immunity characteristics and an operation margin, a method of writing a power supply potential to a memory cell connected to the word line by applying a voltage equal to or higher than a power supply potential plus a threshold voltage to a word line, that is, a word line The boost system is adopted. FIG. 7 shows a conventional semiconductor memory device using the word line boosting method. In FIG. 7, CW
Is the wiring capacitance of the word line W, and the value of the wiring capacitance CW is several pF. C4 is the wiring capacitance of the output line A for boosting the word line W, and the value of the wiring capacitance of C4 is much larger than the value of the wiring capacitance of CW. C1 is a capacitor for boosting the output line A to (power supply voltage Vcc + threshold voltage Vth) or more. The value of the capacitance of C1 is larger than the value of the wiring capacitance C4 of the output line A. It is. In this semiconductor memory device, as shown in the timing chart of FIG. 8, during the precharge period, the precharge signal / PRE goes to H level and the transistor TN
1 turns on, and the capacitor C1 is precharged to the power supply potential Vcc. At this time, the wiring capacitance C4 of the output line A is also charged to the power supply potential Vcc. At this time, the enable signal HVALID and the decode signals AiR and AjR of the decoder circuit are both at the L level, the word line W and the output line A are not connected, and the word line W is grounded. ,
It is at ground potential. When the precharge period ends, the precharge signal / PRE goes to L level. Next, the enable signal XVALID becomes H level and pushes up one electrode potential of the capacitor C1 through two inverters. Therefore, the capacitor C1 supplies a charge to the wiring capacitance C4 of the output line A, and the output line A has a potential equal to or higher than (power supply voltage Vcc + threshold voltage Vth). Next, the decode signals AiR and AjR also go to the H level, the word line W becomes non-ground, and the word line W is connected to the output line A, and the word line W becomes (power supply potential Vcc + threshold voltage). Vth)
The voltage is raised to the above potential.

[Problems to be solved by the invention]

By the way, in the conventional semiconductor memory device, every time the word line W is selected, the wiring capacitance C of the word line W is changed.
Not only does the charge of W (several pF) move, but also the capacitor C
The charge of 1 also moves to the wiring capacitance C4 of the output line A. Therefore, the electric charge corresponding to about 50 pF of CW + C1 + C4 moves, so that there is a problem that current consumption increases. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device using a word line boosting method that consumes less current.

[Means for Solving the Problems]

To achieve the above object, a semiconductor memory device according to the present invention includes, when a word line is selected, an output line connected to the word line via a switching element to boost the potential of the word line, and a power supply line. A charging circuit that is provided between the output lines and charges a potential of the output line to a predetermined first potential that is equal to or lower than a power supply potential Vcc; and supplies a charge to the output line to change the potential of the output line to A booster circuit for boosting the potential of the output line to a predetermined second potential higher than the first potential, and detecting the potential of the output line to raise the potential of the output line to (power supply potential Vcc + threshold voltage V
and a boosted potential detecting circuit for controlling the boosting circuit so as to maintain the voltage at a constant voltage equal to or higher than th).

[Action]

According to the configuration, the output line for boosting the word line to a predetermined potential is supplied with the electric charge from the boosting circuit and boosts the voltage. At this time, the boosted voltage detection circuit detects the potential of the output line and changes the potential of the output line to (power supply voltage
The booster circuit is controlled so as to maintain a constant potential equal to or higher than (Vcc + threshold voltage Vth). Therefore, the potential of the output line is maintained at the constant potential. Therefore, each time the word line is connected to the output line, only the charge corresponding to the wiring capacitance of the word line is supplied from the booster circuit to the word line via the output line,
The charge corresponding to the wiring capacitance of the output line maintained at a constant potential and the charge corresponding to the capacitance of another capacitor connected to the output line do not move. For this reason, power consumption is suppressed.

【Example】

Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 is a circuit diagram of a word line boosting type semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, CW1
Is the wiring capacitance of the word line W1, and the value of this wiring capacitance is several pF. C2 is a capacitor including the wiring capacitance of the output line B. The value of the capacitance of C2 is about several tens of pF, which is considerably larger than the wiring capacitance CW1 of the word line W1. Further, the booster circuit 1 has a function of supplying charges to the output line B to boost the potential of the output line B. The booster circuit 1 has the configuration shown in FIG. Then, a potential detection circuit as a boosted potential detection circuit detects the potential of the output line B so that the potential of the output line B is maintained at a predetermined potential equal to or higher than (power supply voltage Vcc + threshold voltage Vth). On / off of the operation of the booster circuit 1 is controlled.
The precharge circuit has the configuration shown in FIG. 5, and charges the output line B to (power supply voltage Vcc-threshold voltage Vth). In addition, the clamp circuit has a sixth
The potential of the output line B is set to (power supply voltage
Vcc + 2Vth). In the above embodiment, during the precharge period, the precharge signal / PRE goes to the H level, and the decode signals AiR and AjR of the decoder circuit and the enable signal XVALID are both low.
At this time, the word line W1 is grounded to the ground potential, and the output line B is disconnected from the word line W1. The output line B is always maintained at a predetermined potential equal to or higher than (power supply voltage Vcc + threshold value Vth) by the booster circuit 1 and the potential detection circuit. Next, when the word line is selected, the precharge signal / PRE goes to L level, the decode signals AiR, AjR of the decoder circuit and the enable signal XVALID both go to H level, and the word line W1 becomes
It becomes non-ground and is connected to the output line B. Output line B
Is calculated by the booster circuit 1 and the potential detection circuit.
The word line W1 connected to the output line B is always maintained at a predetermined potential equal to or higher than (power supply voltage Vcc + threshold voltage Vth) because it is maintained at a predetermined potential equal to or higher than (power supply voltage Vcc + threshold voltage Vth). Potential. At this time, the word line W1 receives a charge corresponding to the wiring capacitance CW1 of the word line W1 from the booster circuit 1 via the output line B. At this time, the output line B
Is always maintained at a constant potential, the electric charge corresponding to the line capacitance of the output line B (several tens of pF) and the electric charge corresponding to the capacitance of the capacitor connected to the output line B (several tens of pF) are equal to the above-mentioned word. Does not move when selecting a line. Therefore, the electric charge that moves when the word line is selected is equivalent to the wiring capacitance CW1 of the word line W1 (several p).
F) is the only charge. Thus, in the above embodiment,
The charge that moves every time a word line is selected is only the charge corresponding to the wiring capacitance CW1 of the word line W1, so that not only the charge corresponding to the wiring capacitance of the word line as in the conventional example but also the charge corresponding to the inter-line capacitance of the output line. In addition, power consumption can be greatly reduced as compared with the case where the electric charge corresponding to the capacitance of the capacitor connected to the output line moves every time the word line is selected. Next, a second embodiment is shown in FIG. This example is
Instead of the booster circuit 1 of the first embodiment, a booster circuit 2
The only difference from the first embodiment is that a booster circuit and a booster circuit 3 are provided. Therefore, the same portions as those in the first embodiment are denoted by the same reference numerals and symbols, and portions different from those in the first embodiment will be mainly described. In the second embodiment, the booster circuit 2 having a large boosting ability connected to the output line B is connected between the signal line to which the enable signal XVALID is input and the output line B, and has a normal boosting ability. And a booster circuit 3. The booster circuit 3 compensates for a decrease in the potential of the word line W1 when the word line W1 operates once every time the word line is selected, within the minimum operation cycle period. In addition, the boosting circuit 2 having a large boosting capability is provided.
Can boost the output line B at high speed when the power is turned on. Next, a third embodiment is shown in FIG. This example is
The booster circuit 3 of the second embodiment and the enable signal XVAL
The only difference from the second embodiment is that a delay circuit, a NAND gate, and an inverter are connected to the signal line to which the ID is input. Therefore, the same portions as those in the above-described second embodiment are denoted by the same reference numerals and symbols, and portions different from the above-described second embodiment will be mainly described. The booster circuit 3 according to the third embodiment includes an enable signal XV
After a certain period of time set by the delay circuit after the ALID switches from the L level to the H level, the operation automatically stops. That is, the booster circuit 3 is connected to the word line
After a certain amount of time elapses after compensating for the potential drop of the word line W1 when W1 operates once, the operation automatically stops. Therefore, the power consumed by the booster circuit 3 can be reduced.

【The invention's effect】

As is apparent from the above description, in the semiconductor memory device according to the present invention, the boosted voltage detection circuit connects the word line to the power supply voltage Vc.
(c + threshold voltage Vth) and a booster circuit for detecting the potential of the output line for boosting the potential to a fixed potential or more and supplying a charge to the output line to boost the output line. Is controlled so as to be maintained at the potential. Therefore, the potential of the output line can be maintained at the constant potential. Therefore, in order to boost the word line to a predetermined potential, each time the word line is connected to the output line, only the charge corresponding to the wiring capacitance of the word line is transferred from the booster circuit through the output line. , May be supplied to the word line. Therefore, according to the present invention, each time a word line is connected to an output line as in the related art, in addition to the charge corresponding to the wiring capacitance of the word line, the charge corresponding to the wiring capacitance of the output line and the output line are connected. The power consumption can be greatly reduced as compared with the case where the charge corresponding to the capacity of the charging capacitor is moved. Further, according to the semiconductor memory device of the present invention, in addition to the booster circuit, a charging circuit provided between the power supply line and the output line for charging the potential of the output line to a predetermined first potential equal to or lower than the power supply potential is provided. Further, since this is provided, there is an effect that the boosting operation of the output line can be performed at a higher speed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the semiconductor memory device of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIG. 3 is a circuit of a third embodiment of the present invention. FIGS. 4 and 5 are circuit diagrams of the booster circuit 1 of the first embodiment, FIG. 5 is a circuit diagram of a precharge circuit of the first embodiment, and FIG. 6 is a clamp of the first embodiment. FIG. 7 is a circuit diagram of a conventional semiconductor memory device, and FIG. 8 is a timing diagram of the conventional semiconductor memory device. W1, W: Word line, CW1, CW: Word line wiring capacitance.

Claims (1)

(57) [Claims] An output line connected to the word line via a switching element for boosting a potential of the word line when the word line is selected; and an output line provided between a power supply line and the output line. A charging circuit for charging the potential of the line to a predetermined first potential equal to or lower than the power supply potential Vcc; and supplying a charge to the output line to raise the potential of the output line to a predetermined level higher than the first potential. A booster circuit for boosting the potential of the output line to 2 and controlling the booster circuit so as to detect the potential of the output line and maintain the potential of the output line at a constant voltage equal to or higher than (power supply potential Vcc + threshold voltage Vth). A semiconductor memory device comprising a boosted potential detection circuit.