KR960036785A - Affine Converter for 3D Graphics Parallel Processing - Google Patents
Affine Converter for 3D Graphics Parallel Processing Download PDFInfo
- Publication number
- KR960036785A KR960036785A KR1019950006625A KR19950006625A KR960036785A KR 960036785 A KR960036785 A KR 960036785A KR 1019950006625 A KR1019950006625 A KR 1019950006625A KR 19950006625 A KR19950006625 A KR 19950006625A KR 960036785 A KR960036785 A KR 960036785A
- Authority
- KR
- South Korea
- Prior art keywords
- image data
- affine
- dimensional image
- dimensional
- output
- Prior art date
Links
- PXFBZOLANLWPMH-UHFFFAOYSA-N 16-Epiaffinine Natural products C1C(C2=CC=CC=C2N2)=C2C(=O)CC2C(=CC)CN(C)C1C2CO PXFBZOLANLWPMH-UHFFFAOYSA-N 0.000 title claims abstract description 14
- 238000012545 processing Methods 0.000 title claims abstract description 5
- 230000009466 transformation Effects 0.000 claims abstract description 5
- 238000006243 chemical reaction Methods 0.000 claims 6
- 238000012805 post-processing Methods 0.000 claims 1
- 239000000872 buffer Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000001131 transforming effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T3/00—Geometric image transformations in the plane of the image
- G06T3/02—Affine transformations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2200/00—Indexing scheme for image data processing or generation, in general
- G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Image Processing (AREA)
Abstract
본 발명은 3차원 그래픽 병렬처리를 위한 아핀변환 장치에 관한 것으로, 프레임 단위로 입력되는 3차원 영상데이타가 4×4, 즉 16개의 부블럭으로 분할되어 16개의 AT연산부에서 AT연산이 병렬처리되며, 카운터에서 16개의 AT연산부의 AT연산횟수가 계수되어 기설정된 소정횟수가 되면 카운터로부터 종료신호가 발생되어 16개의 버퍼에 각각 저장되어 있는 부블럭의 3차원 영상데이타가 최종적으로 출력되고, 후처리부에서 2차원 이미지로서 좌표변환되어 모니터에 디스플레이되므로써, 애니매이션 풍경용 3차원 그래픽 처리를 고속으로 처리할 수 있도록 한 것이다.The present invention relates to an affine transformation apparatus for 3D graphics parallel processing, wherein 3D image data input in units of frames is divided into 4 × 4, that is, 16 sub-blocks, so that AT operations are processed in 16 AT operations in parallel. When the AT operation count of the 16 AT calculation units is counted by the counter and the predetermined number of times is set, the end signal is generated from the counter, and the 3D image data of the sub-blocks stored in the 16 buffers is finally output. By transforming the coordinates as a two-dimensional image, and displaying them on a monitor, it is possible to process three-dimensional graphics for an animated landscape at high speed.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 본 발명의 바람직한 실시예에 따라 3차원 그래픽 병렬처리를 위한 아핀변환 장치의 개략적인 블럭구성도, 제2도는 제1도의 각 AT연산부의 상세도, 제3도는 본 발명에 일예로서 프레임별 3차원 영상 신호를 4×4의 부블럭으로 분할한 것을 도시한 도면.1 is a schematic block diagram of an affine transformation apparatus for three-dimensional graphics parallel processing according to a preferred embodiment of the present invention, FIG. 2 is a detailed view of each AT operation unit of FIG. 1, and FIG. 3 is a frame as an example of the present invention. 3D video signal divided into 4x4 subblocks.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950006625A KR0181058B1 (en) | 1995-03-28 | 1995-03-28 | Affine transformer for parallel processing the 3-dimension graphics |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950006625A KR0181058B1 (en) | 1995-03-28 | 1995-03-28 | Affine transformer for parallel processing the 3-dimension graphics |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960036785A true KR960036785A (en) | 1996-10-28 |
KR0181058B1 KR0181058B1 (en) | 1999-05-01 |
Family
ID=19410659
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950006625A KR0181058B1 (en) | 1995-03-28 | 1995-03-28 | Affine transformer for parallel processing the 3-dimension graphics |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0181058B1 (en) |
-
1995
- 1995-03-28 KR KR1019950006625A patent/KR0181058B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0181058B1 (en) | 1999-05-01 |
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