KR960036069A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
KR960036069A
KR960036069A KR1019950006823A KR19950006823A KR960036069A KR 960036069 A KR960036069 A KR 960036069A KR 1019950006823 A KR1019950006823 A KR 1019950006823A KR 19950006823 A KR19950006823 A KR 19950006823A KR 960036069 A KR960036069 A KR 960036069A
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KR
South Korea
Prior art keywords
forming
charge storage
bit line
electrode
film
Prior art date
Application number
KR1019950006823A
Other languages
Korean (ko)
Inventor
황준
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950006823A priority Critical patent/KR960036069A/en
Publication of KR960036069A publication Critical patent/KR960036069A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 제조방법에 관한것으로서, 비트라인이 전하저장전극 보다 나중에 형성되는 반도체소자에서 비트라인 콘택을 공유하는 인접한 셀의 전하저장전극을 하나의 패턴으로 형성하고, 이를 비트라인 콘택홀 형성공정에 분리시켜 전하저장전극의 표면적을 증가시켰으므로, 정전용량이 증가되어 소자동작의 신뢰성이 향성되고, 공정이 간단하여 공정 수율이 향상된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein in a semiconductor device in which bit lines are formed later than the charge storage electrodes, the charge storage electrodes of adjacent cells sharing the bit line contacts are formed in one pattern, and the bit line contact holes are formed. Since the surface area of the charge storage electrode is increased by separation from the forming process, the capacitance is increased to improve the reliability of the device operation, and the process is simple and the process yield is improved.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 반도체소자의 레이아웃도, 제4A도 내지 제4D도는 제3도에 도시되어 있는 반도체소자의 제조공정도로서, 제3도에서의 선 B-B에 따른 단면을 도시한 도면.FIG. 3 is a layout diagram of the semiconductor device according to the present invention, and FIGS. 4A to 4D are manufacturing process diagrams of the semiconductor device shown in FIG. 3, showing a cross section taken along the line B-B in FIG.

Claims (4)

소자분리 산화막과 게이트산화막이 형성되어 있는 반도체기판상에 일련의 게이트전극들을 형성하는 공정과, 상기 게이트전극들을 양측의 반도체기판에 소오스/드레인전극을 형성하는 공정과, 상기 구조의 표면에 제1층간절연막을 도포하는 공정과, 상기 소오스/드레인전극에서 전하저장전극 콘택으로 예정되어 있는 부분 상측의 제1층간절연막을 제거하여 전하저장전극 콘택홀을 형성하는 공정과, 상기 콘택홀들을 메우는 전하저장전극을 형성하되 하나의 비트라인 콘택을 공유하는 전하저장전극은 서로 연결하도록 패터닝하는 공정과, 상기 전하저장전극의 상부에 유전막을 형성하는 공정과, 상기 전하저장전극상에 플레이트 전극을 형성하는 공정과, 상기 구조의 전표면에 제2층간절연막을 형성하는 공정과, 상기 소오스/드레인전극에서 비트라인 콘택으로 예정되어 있는 부분 상측의 제2층간절연막에서 제1층간절연막까지 순차적으로 제거하여 비트라인 콘택홀을 형성하되 상기 서로 연결되어 전하저장전극을 서로 분리 시키는 공정과, 상기 비트라인 콘택홀의 측벽에 절연 스페이서를 형성하는 공정과, 상기 비트라인 콘택홀을 메우는 비트라인을 형성하는 공정을 구비하는 반도체소자의 제조벙법.Forming a series of gate electrodes on a semiconductor substrate on which a device isolation oxide film and a gate oxide film are formed, forming a source / drain electrode on the semiconductor substrate on both sides, and forming a first electrode on the surface of the structure Forming a charge storage electrode contact hole by removing an interlayer insulating film from the source / drain electrode, and removing a first interlayer insulating film on the upper portion of the source / drain electrode that is intended as a charge storage electrode contact; Forming an electrode but patterning the charge storage electrodes sharing one bit line contact so as to be connected to each other, forming a dielectric layer on the charge storage electrode, and forming a plate electrode on the charge storage electrode Forming a second interlayer insulating film on the entire surface of the structure; and forming a bit line at the source / drain electrodes. Forming a bit line contact hole by sequentially removing the second interlayer insulating film on the upper part of the contact portion to the first interlayer insulating film, wherein the bit line contact holes are connected to each other, and the charge storage electrodes are separated from each other; A method of manufacturing a semiconductor device comprising the step of forming an insulating spacer and the step of forming a bit line filling the bit line contact hole. 제1항에 있어서, 상기 전하저장전극 및 비트라인을 다결정실리콘으로 형성하는 것을 특징으로하는 반도체소자의 제조방법.The method of claim 1, wherein the charge storage electrode and the bit line are formed of polycrystalline silicon. 제1항에 있어서, 상기 유전막을 산화막 또는 질화막의 단층이거나. 산화막-질화막-산화막의 적층 구조로 형성하는 것을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the dielectric film is a single layer of an oxide film or a nitride film. A method of manufacturing a semiconductor device, characterized by forming an oxide film-nitride film-oxide film in a stacked structure. 제1항에 있어서, 상기 스페이서를 산화막 또는 질화막으로 형성하는 것을 특징으로 하는 반도체소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the spacer is formed of an oxide film or a nitride film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950006823A 1995-03-29 1995-03-29 Manufacturing method of semiconductor device KR960036069A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950006823A KR960036069A (en) 1995-03-29 1995-03-29 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950006823A KR960036069A (en) 1995-03-29 1995-03-29 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
KR960036069A true KR960036069A (en) 1996-10-28

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KR1019950006823A KR960036069A (en) 1995-03-29 1995-03-29 Manufacturing method of semiconductor device

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