KR980006268A - Semiconductor memory device formed of ferroelectric transistor storage cell and manufacturing method thereof - Google Patents

Semiconductor memory device formed of ferroelectric transistor storage cell and manufacturing method thereof Download PDF

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Publication number
KR980006268A
KR980006268A KR1019960020365A KR19960020365A KR980006268A KR 980006268 A KR980006268 A KR 980006268A KR 1019960020365 A KR1019960020365 A KR 1019960020365A KR 19960020365 A KR19960020365 A KR 19960020365A KR 980006268 A KR980006268 A KR 980006268A
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South Korea
Prior art keywords
ferroelectric
gate electrode
transistor
semiconductor substrate
switching transistor
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KR1019960020365A
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Korean (ko)
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KR0183878B1 (en
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이기홍
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김광호
삼성전자 주식회사
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Publication of KR980006268A publication Critical patent/KR980006268A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

신규한 강유전체 메모리장치 및 그 제조방법이 개시되어 있다. 반도체기판에 제공된 소오스 및 드레인 영역들과, 상기 소오스 영역과 드레인 영역 사이의 상기 반도체기판을 식각하여 형성된 트렌치의 내벽을 따라 형성된 강유전체막과, 상기 강유전체막 상에 형성된 제1게이트전극을 갖는 강유전체 트랜지스터; 및 상기 강유전체 트랜지스터에 인접한 상기 반도체기판에 제공된 채널 영역과, 상기 채널 영역 상에 게이트 절연막을 개재하여 형성된 제2 게이트전극을 갖는 스위칭 트랜지스터를 구비한다. 단순하고 용이한 공정으로 제조 단가가 낮고 소자 특성이 우수한 강유전체 메모리장치를 제공할 수 있다.A novel ferroelectric memory device and a manufacturing method thereof are disclosed. A ferroelectric transistor having source and drain regions provided on a semiconductor substrate, a ferroelectric film formed along an inner wall of a trench formed by etching the semiconductor substrate between the source and drain regions, and a first gate electrode formed on the ferroelectric film. ; And a switching transistor having a channel region provided in the semiconductor substrate adjacent to the ferroelectric transistor, and a second gate electrode formed on the channel region via a gate insulating film. It is possible to provide a ferroelectric memory device having low manufacturing cost and excellent device characteristics by a simple and easy process.

Description

강유전체 트랜지스터 스토리지 셀로 형성된 반도체 메모리장치 및 그 제조방법Semiconductor memory device formed of ferroelectric transistor storage cell and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1도는 종래의 강유전체 메로리장치의 셀 구조를 나타내는 단면도1 is a cross-sectional view showing the cell structure of a conventional ferroelectric memory device.

Claims (3)

반도체 기판에 게공된 소오스 및 드레인 영역들과, 상기 소오스 영역과 드레인 영역 사이의 상기 반도체기판을 식각하여 형성된 트렌치의 내벽을 따라 형성된 강유전체막과, 상기 강유전체막 상에 형성된 제1게이트전극을 갖는 강유전체 트랜지스터; 및 상기 강유전체 트랜지스터에 인접한 상기 반도체기판에 제공된 채널영역과, 상기 채널 영역 상에 게이트절연막을 개재하여 형성된 제2게이트전극을 갖는 스위칭 트랜지스터를 구비하는 것을 특징으로 하는 반도체 메모리장치A ferroelectric having source and drain regions formed in the semiconductor substrate, a ferroelectric film formed along an inner wall of a trench formed by etching the semiconductor substrate between the source and drain regions, and a first gate electrode formed on the ferroelectric film. transistor; And a switching transistor having a channel region provided in the semiconductor substrate adjacent to the ferroelectric transistor and a second gate electrode formed on the channel region via a gate insulating film. 제1항에 있어서, 상기 스위칭 트랜지스터의 제2게이트전극을 연결하는 제1워드라인, 상기 강유전체 트랜지스터의 제1게이트전극을 연결하는 제2워드라인 상기 강유전체 트랜지스터 또는 스위칭 트랜지스터의 어느 하나의 드레인 영역을 연결하는 비트라인 및 상기 강유전체 트랜지스터 또는 스위칭 트랜지스터의 어느 하나의 소오스 영역을 연결하는 소오스라인을 더 구비하는 것을 특징으로 하는 반도체 메모리 장치2. The drain of any one of the ferroelectric transistor and the switching transistor of claim 1, wherein the first word line connects the second gate electrode of the switching transistor, and the second word line connects the first gate electrode of the ferroelectric transistor. And a bit line for connecting and a source line for connecting one source region of the ferroelectric transistor or the switching transistor. 제1도전형의 반도체기판 상에 소자분리영역을 형성하여 활성영역을 정의하는 단계; 상기 반도체기판의 활성영역을 소정깊이로 식각하여 트렌치를 형성하는 단계; 상기 트렌치가 형성된 결과물 전면에 강유전체막을 증착하고, 사진식각 공정으로 상기 트렌치 이외의 부분에 증착된 상기 강유전체를 제거하는 단계; 상기 결과물 전면에 게이트절연막 및 제1도전층을 차례로 형성하는 단계; 및 사진공정으로 스위칭 트랜지스터의 게이트전극이 형성될 부분을 마스킹하고 상기 제1도전층을 에치백함으로써, 강유전체 트랜지스터의 제1게이트전극과 스위칭 트랜지스터의 제2게이트전극을 형성함과 동시에, 상기 제1 및 제2게이트전극을 서로 절연시키는 단계를 구비하는 것을 특징으로 하는 반도체 메모리장치의 제조방법Forming an isolation region on the first conductive semiconductor substrate to define an active region; Etching the active region of the semiconductor substrate to a predetermined depth to form a trench; Depositing a ferroelectric film on the entire surface of the resultant trench, and removing the ferroelectric deposited on portions other than the trench by a photolithography process; Sequentially forming a gate insulating film and a first conductive layer on the entire surface of the resultant product; And masking a portion where the gate electrode of the switching transistor is to be formed in the photolithography process and etching back the first conductive layer, thereby forming a first gate electrode of the ferroelectric transistor and a second gate electrode of the switching transistor, and simultaneously And insulating the second gate electrode from each other.
KR1019960020365A 1996-06-07 1996-06-07 Semiconductor memory device composed of ferroelectric substance transistor storage cell and its manufacturing method KR0183878B1 (en)

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KR1019960020365A KR0183878B1 (en) 1996-06-07 1996-06-07 Semiconductor memory device composed of ferroelectric substance transistor storage cell and its manufacturing method

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KR1019960020365A KR0183878B1 (en) 1996-06-07 1996-06-07 Semiconductor memory device composed of ferroelectric substance transistor storage cell and its manufacturing method

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KR0183878B1 KR0183878B1 (en) 1999-03-20

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KR101950002B1 (en) * 2012-07-30 2019-02-20 에스케이하이닉스 주식회사 Semiconductor device and method for fabricating the same

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