KR960036015A - Method for manufacturing MOS transistor of LDD structure - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS transistor having an LDD structure, and more particularly, to a method for manufacturing a MOS transistor having an LDD structure that prevents a hot carrier phenomenon, forms a shallow junction, and forms a silicide film on an electrode and a junction. In the LDD structure to prevent the device, the degree of integration of the device is remarkably increased, and there is still a problem of hot carriers. Also, in the subsequent metal wiring process, the contact resistance of the electrode is increased to generate a leakage current at the junction, thereby increasing the reliability of the device. In the present invention, the gate sidewall spacer of the conventional LDD structure is used as an etch barrier layer, and the gate electrode, the source and the drain junction are etched to a predetermined depth to form a shallow junction transistor corresponding to the highly integrated device. Contact during metal wiring process Titanium silicide is formed on top of the electrode and the junction to reduce hot carriers in the device, and the contact resistance is reduced due to the titanium silicide film, and the electrical current of the device can be improved by suppressing leakage current at the junction. .

Description

Method for manufacturing MOS transistor of LDD structure

As this is a public information case, the full text was not included.

2 to 5 are cross-sectional views of essential parts of a MOS transistor according to an embodiment of the present invention.

Claims (7)

In the method of manufacturing a MOS transistor of an LDD structure in which a gate electrode is formed on a semiconductor substrate, low concentration ion implantation is formed, a spacer is formed, high concentration ion implantation is performed, and metal wiring is formed, the high concentration ion implantation is performed. And etching a gate electrode and a source drain junction to a predetermined depth, and then forming a silicide layer on the etched gate electrode and the source and drain junctions. The method of claim 1, wherein after the high concentration of ion implantation, heat treatment is performed at a temperature of 800 to 900 ° C. for 35 to 45 minutes. 3. The method of claim 1, wherein the gate electrode and the source drain junction are etched and formed by a thickness of 400 to 600 kV. 4. The method of claim 1 or 2, wherein a titanium film is deposited by about 100 to 500 kV in order to form the silicide film, followed by heat treatment. The method of claim 4, wherein the heat treatment is performed at 65 ° C. for 30 seconds at a low temperature for a short time. The method of claim 1, wherein the low concentration ions are implanted with phosphorus ions at a concentration of 6 × 10 ¹³ to 1 × 20 ¹³ cm ⁻² and an energy of 150 to 170 KeV. The MOS transistor of claim 1 or 6, wherein the high concentration ions are implanted with fluorine ions at a concentration of 5 × 10 ¹⁵ to 7 × 10 ¹⁵ cm ^-2 and an energy of 80 to 100 KeV. Manufacturing method. ※ Note: The disclosure is based on the initial application.