KR960035936A - Flange Up Stage for Large Chips in Semiconductor Equipment - Google Patents

Flange Up Stage for Large Chips in Semiconductor Equipment Download PDF

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Publication number
KR960035936A
KR960035936A KR1019950007548A KR19950007548A KR960035936A KR 960035936 A KR960035936 A KR 960035936A KR 1019950007548 A KR1019950007548 A KR 1019950007548A KR 19950007548 A KR19950007548 A KR 19950007548A KR 960035936 A KR960035936 A KR 960035936A
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KR
South Korea
Prior art keywords
flange
stage
semiconductor
chip
large chips
Prior art date
Application number
KR1019950007548A
Other languages
Korean (ko)
Other versions
KR0145126B1 (en
Inventor
장석홍
박윤
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950007548A priority Critical patent/KR0145126B1/en
Publication of KR960035936A publication Critical patent/KR960035936A/en
Application granted granted Critical
Publication of KR0145126B1 publication Critical patent/KR0145126B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

본 발명은 반도체 제조공정에서 웨이퍼 절단공정후 반도체 칩에 접착되어 있는 테이프를 분리하기 위한 플렌지-업 스테이지에 관한 것으로, 다이접착공정에서 사용되는 플렌지-업 스페이지(Plunge-up Stage)의 표면에 웨이퍼상의 칩에 접착된 테이프를 자동으로 분리할 수 있는 봉을 설치하여 반도체 집적회로의 오픈 또는 쇼트되는 불량을 방지하고, 테이프의 안정된 분리로 칩이 떨어져 깨지는 현상등을 방지하여 생산성 향상 및 원가절감은 물론 고품질의 제품을 제조하기 위한 반도체 장비의 대형칩용 플렌지-업 스페이지를 제공하기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flange-up stage for separating a tape adhered to a semiconductor chip after a wafer cutting process in a semiconductor manufacturing process. The present invention relates to a surface of a flange-up stage used in a die bonding process. Improved productivity and cost savings by installing a rod that can automatically separate the tapes attached to the chip on the wafer to prevent defects such as opening or shorting of semiconductor integrated circuits and preventing chip breakage due to stable separation of the tape. In addition, it aims to provide a flange-up page for large chips in semiconductor equipment for manufacturing high quality products.

Description

반도체 장비의 대형칩용 플렌지 업 스테이지Flange Up Stage for Large Chips in Semiconductor Equipment

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의한 실시예로서, 웨이퍼 상의 칩을 플렌지 스테이지에서 테이프로 부터 분리하는 상태를 나타낸 실시예시도, 제4도는 본 발명의 플렌지-업 스페이지의 표면을 예시한 확대 평면도.3 is an embodiment according to the present invention, showing an embodiment in which the chip on the wafer is separated from the tape in the flange stage, and FIG. 4 is an enlarged plan view illustrating the surface of the flange-up page of the present invention.

Claims (3)

반도체 다이 접착 장비의 플렌지-업 스테이지에 있어서,스테이지의 표면에 봉을 엇갈리게 설치하되, 제1봉에 대하여 제2봉이 양쪽으로 위치 하도록 설치된 것을 특징으로 하는 반도체 장비의 대형칩용 플렌지-업 스테이지.A flange-up stage of a semiconductor die bonding equipment, wherein the rods are alternately installed on the surface of the stage, but the second rods are positioned to both sides with respect to the first rod. 제1항에 있어서, 상기 플렌지-업 스테이지의 표면에 설치된 봉은 1.0mm의 직경을 갖는 것을 특징으로 한느 반도체 장비의 대형칩용 플렌지-업 스테이지.The flange-up stage of claim 1, wherein the rod installed on the surface of the flange-up stage has a diameter of 1.0 mm. 제1항에 있어서, 상기 봉은 일체형 또는 분리형 임을 특징으로 하는 반도체 장비의 대형칩용 플렌지업 스테이지.The flange up stage of claim 1, wherein the rod is integrated or separated. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950007548A 1995-03-31 1995-03-31 A plunge-up stage used in large scale chip of semiconductor apparatus KR0145126B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950007548A KR0145126B1 (en) 1995-03-31 1995-03-31 A plunge-up stage used in large scale chip of semiconductor apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950007548A KR0145126B1 (en) 1995-03-31 1995-03-31 A plunge-up stage used in large scale chip of semiconductor apparatus

Publications (2)

Publication Number Publication Date
KR960035936A true KR960035936A (en) 1996-10-28
KR0145126B1 KR0145126B1 (en) 1998-08-17

Family

ID=19411332

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950007548A KR0145126B1 (en) 1995-03-31 1995-03-31 A plunge-up stage used in large scale chip of semiconductor apparatus

Country Status (1)

Country Link
KR (1) KR0145126B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102127695B1 (en) * 2019-12-20 2020-06-29 위재우 Semiconductor die detachment apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102127695B1 (en) * 2019-12-20 2020-06-29 위재우 Semiconductor die detachment apparatus

Also Published As

Publication number Publication date
KR0145126B1 (en) 1998-08-17

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