KR960033086A - Pseudo-synchronous signal generation circuit of image display device - Google Patents

Pseudo-synchronous signal generation circuit of image display device Download PDF

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KR960033086A
KR960033086A KR1019950002728A KR19950002728A KR960033086A KR 960033086 A KR960033086 A KR 960033086A KR 1019950002728 A KR1019950002728 A KR 1019950002728A KR 19950002728 A KR19950002728 A KR 19950002728A KR 960033086 A KR960033086 A KR 960033086A
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pseudo
signal
synchronization signal
synchronous signal
image
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KR1019950002728A
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KR0145914B1 (en
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철 김
강재봉
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배순훈
대우전자 주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/06—Generation of synchronising signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/44504—Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/63—Generation or supply of power specially adapted for television receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/12—Picture reproducers
    • H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
    • H04N9/3179—Video signal processing therefor

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Graphics (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

본 발명은 화상표시장치의 의사동기신호 생성회로에 관한 것으로, 투사형 화상표시장치에 적용되어 화상신호가 입력되지 않는 상태에서도 내부적으로 발생된 수평동기신호를 이용하여 OSD정보(on screen display)표시 및 또는 배경화면의 표시를 위해 필요한 의사동기신호(특히 수직동기신호)를 생성하기 위해, 동기신호분리부(13)에 의해 동기신호가 검출되지 않는 화상신호의 비입력시 배경화면 및/또는 OSD문자정보의 표시를 제어하는 제어부(18)의 제어하에 상기 화상신호의 비입력시 수직동기신호를 의사적으로 생성하여 상기 배경화면 및/또는 OSD문자정보의 표시가 가능하도록 하기 위한 의사동기신호 생성회로부(17)를 포함하여 구성되며, 상기 의사동기신호 생성회로부(17)는 의사수평동기신호를 16진카운트하여 의사수직동기신호를 생성하는 의사동기신호 생성부(200)와, 상기 화상신호의 비입력시 상기 의사동기신호 생성부(200)에서 생성된 의사수직동기 신호를 스위칭출력하는 스위칭부(100)를 갖추어 이루어진 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo-synchronous signal generating circuit of an image display apparatus, and is applied to a projection type image display apparatus to display OSD information using an internally generated horizontal synchronization signal even when no image signal is input. Alternatively, in order to generate a pseudo-synchronization signal (especially a vertical synchronization signal) necessary for displaying a background screen, the background screen and / or the OSD character upon non-input of an image signal for which a synchronization signal is not detected by the synchronization signal separation unit 13. Pseudo-synchronization signal generation circuit unit for generating the vertical synchronization signal pseudo-generating the non-input of the image signal under the control of the control unit 18 that controls the display of information to enable the display of the background screen and / or OSD text information. And a pseudo synchronous signal generation circuit unit 17 to generate a pseudo vertical synchronous signal by hexadecimal counting the pseudo horizontal synchronous signal. A signal generator 200 and a switching unit 100 for switching the pseudo-vertical synchronous signal generated by the pseudo synchronous signal generator 200 when the image signal is not inputted.

Description

화상표시장치의 의사동기신호 생성회로Pseudo-synchronous signal generation circuit of image display device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 바람직한 예에 따른 의사동기신호 생성회로가 채용되어 배경화면/OSD문자정보의 표시가 가능한 투사형 화상표시장치의 개략적인 블럭구성을 나타낸 도면2 is a schematic block diagram of a projection type image display apparatus capable of displaying a background image / OSD character information by employing a pseudo synchronous signal generation circuit according to a preferred embodiment of the present invention.

Claims (6)

광변조방식으로 입력화상신호를 광변조하는 광변조수단(23)과, 그 광변조수단(23)에 의한 광변조를 행/열방향에서 구동제어하는 행/열구동수단(24,25), 상기 입력화상신호에서 동기신호를 분리하는 동기신호분리수단(13), 그 동기신호분리수단(13)에서 검출된 동기신호를 기초로 화상표시를 위한 화상보정데이터저장수단(14,15)에 저장된 화상보정데이터의 처리를 위한 어드레스/ 제어신호생성수단(12), 상기 화상신호와 화상보정데이터를 가산처리하여 보정된 화상보정데이터를 생성하는 화상보정수단(16)을 갖추어 구성된 투사형 화상표시장치에 있어서, 상기 동기신호분리수단(13)에 의해 동기신호가 검출되지 않는 화상신호의 비입력시 배경화면 및/ 또는 OSD문자정보의 표시를 제어하는 제어수단(18)의 제어하에 상기 화상신호의 비입력시 수직동기신호를 의사적으로 생성하여 상기 배경화면 및/또는 문자정보의 표시가 가능하도록 하기 위한 의사동기신호 생성수단(17)을 포함하여 구성되며, 상기 의사동기신호 생성수단(17)은 의사수평동기신호를 16진카운트하여 의사수직동기신호를 생성하는 의사동기신호 생성부(200)와, 상기 화상신호의 비입력시 상기 의사동기신호 생성부(200)에서 생성된 의사주식동기신호를 스위칭출력하는 스위칭부(100)를 갖추어 구성된 것을 특징으로 하는 화상표시장치의 의사동기신호 생성회로.Optical modulation means 23 for optically modulating the input image signal by the optical modulation method, row / column driving means 24, 25 for driving control of optical modulation by the optical modulation means 23 in the row / column direction, Stored in the image correction data storage means (14, 15) for image display based on the synchronization signal separation means (13) for separating the synchronization signal from the input image signal, and the synchronization signal detected by the synchronization signal separation means (13). A projection type image display apparatus comprising an address / control signal generating means 12 for processing image correction data, and image correction means 16 for adding the image signal and the image correction data to generate corrected image correction data. The ratio of the image signal under the control of the control means 18 for controlling the display of the background image and / or the OSD character information during the non-input of the image signal for which the synchronization signal is not detected by the synchronization signal separating means 13 Vertical sync signal at input And a pseudo synchronous signal generating means 17 for pseudo-generating and enabling displaying of the background image and / or text information. The pseudo synchronous signal generating means 17 generates a pseudo horizontal synchronous signal. A pseudo synchronous signal generator 200 for generating a pseudo vertical synchronous signal by generating a true count, and a switching unit for switching out a pseudo stock synchronous signal generated by the pseudo synchronous signal generator 200 when the image signal is not inputted ( And a pseudo synchronous signal generating circuit of the image display apparatus. 제1항에 있어서, 상기 의사동기신호 생성수단(17)의 의사동기신호 생성부(200)는 의사적인 수평동기신호를 수직동기신호의 주기에 걸쳐 16진카운트하여 그 카운트결과를 의사수직동기신호로서 생성하는 제1 내지 제3 카운너(201,207, 215)와, 상기 제1 및 제2카운터(201, 207, 215)의 카운트결과를 논리처리하는 제1논리게이트(213), 상기 제1논리게이트(213)의 출력과 상기 제3카운터(215)의 카운트결과를 논리처리하여 의사수직동기신호로서 출력하는 제2논리게이트(221)로 구성되고, 그 제1 내지 제3카운터(201, 207, 215)에 대해서는 상기 수직동기신호의 주기를 16진수로 환산하여 할당하는 자리에 대한 카운트를 실행하여 그 카운트의 종료시 카운트결과를 의사수직동기신호로서 출력하도록 된 것을 특징으로 하는 화상표시장치의 의사동기신호 생성회로.2. The pseudo synchronous signal generator 200 of the pseudo synchronous signal generating means 17 hexadecimal counts a pseudo horizontal synchronous signal over a period of a vertical synchronous signal, and counts the result of the pseudo vertical synchronous signal. First to third counters 201, 207, and 215 to be generated as a first logic gate, and a first logic gate 213 and a first logic to logically count results of the first and second counters 201, 207, and 215. And a second logic gate 221 which logically processes the output of the gate 213 and the count result of the third counter 215 and outputs it as a pseudo-vertical synchronous signal. The first to third counters 201 and 207 And 215, a count is performed for the digits in which the period of the vertical synchronization signal is converted to hexadecimal, and the count result is output as a pseudo vertical synchronization signal at the end of the count. Synchronization signal generation circuit. 제2항에 있어서, 상기 제1카운터(201)는 상기 수직동기신호의 주기(즉, 의사수평동기신호의 펄스 수)에 대한 16진 데이터 중 최하위 자리수를 카운트하도록 클럭단(CLK)이 의사수평동기신호에 의해 클럭제어되고 제1내지 제3입력단 (A1,B1,C1)은 상기 접지전위( GND)에 접속되며 제4입력단(D1)은 전원전위(Vcc)에 접속되어 그 초기치가 '8'(16진수)로 설정되고 그 초기치로부터 '7'(16진수)을 카운트하여 하이레벨의 카운트결과 (즉, 캐리(carry))를 출력하도록 구성된 것을 특징으로 하는 화상표시장치의 의사동기신호 생성회로.The clock stage CLK of claim 2, wherein the first counter 201 counts the least significant digit of the hexadecimal data for the period of the vertical synchronization signal (ie, the number of pulses of the pseudo horizontal synchronization signal). The clock is controlled by the synchronization signal, and the first to third input terminals A1, B1, and C1 are connected to the ground potential GND, and the fourth input terminal D1 is connected to the power source potential Vcc, and its initial value is' 8. Is set to '(hexadecimal) and counts' 7' (hexadecimal) from its initial value to generate a high level count result (i.e. a carry). Circuit. 제2항에 있어서, 상기 제2카운터(207)는 상기 수직동기신호의 16진 데이터에 대한 중간 자리수를 카운트 하도록 클럭단(CLK)이 의사수평동기신호에 의해 클럭제어되고 제1 내지 제4입력단(A2, ..., D2)은 상기 전원전위(Vcc)에 접속되며 제5입력단(END)은 상기 제1카운터(201)의 하이레벨출력에 접속되어 그 초기치가 'F'(16진수)로 설정되고 상기 제1카운터(201)로부터 하이레벨의 카운트결과가 인가되는 경우 하이레벨의 카운트결과 (캐리)를 출력하도록 구성된 것을 특징으로 하는 화상표시장치의 의사동기신호 생성회로.3. The second counter 207 is configured such that the clock stage CLK is clock-controlled by a pseudo horizontal synchronization signal to count intermediate digits of the hexadecimal data of the vertical synchronization signal, and the first to fourth input terminals. (A2, ..., D2) is connected to the power supply potential Vcc and the fifth input terminal END is connected to the high level output of the first counter 201, and its initial value is 'F' (hexadecimal). And a high level count result (carrie) when the high level count result is applied from the first counter (201). 제2항에 있어서, 상기 제3카운터(215)는 상기 16진수로 환산된 수직동기신호의 주기에 대한 최상위 자리수를 카운트하도록 클럭단(CLK)이 수평동기신호에 의해 클럭제어되고 제1입력단(A3)은 상시 접지전위(GND)에 접속되고, 제2 내지 제4입력단 (B3,C3,D3)은 상기 전원전위(Vcc)에 접속되며 제5입력단(END)은 상기 제2카운터(207)의 하이레벨출력에 접속되고 그 초기치가 'E'(16진수)로 설정되고 상기 제2카운터(207)로부터 하이레벨의 카운트결과에 따라 16진 카운트를 실행하여 하이레벨의 카운트결과(캐리)를 출력하도록 구성된 것을 특징으로 하는 화상표시장치의 의사동기신호 생성회로.The clock counter CLK is clock-controlled by the horizontal synchronization signal to count the most significant digit of the period of the vertical synchronization signal converted into hexadecimal. A3) is connected to the ground potential GND, second to fourth input terminals B3, C3, and D3 are connected to the power source potential Vcc, and a fifth input terminal END is connected to the second counter 207. Is connected to the high level output of < RTI ID = 0.0 > and < / RTI > its initial value is set to " E " And a pseudo synchronous signal generation circuit of the image display apparatus. 제1항에 있어서, 상기 의사동기신호 생성수단(17)의 스위칭부(100)는 일단이 상기 화상신호에서 분리된 수직동기신호에 접속되고 다른 단이 상기 의사적으로 생성되는 수직동기신호에 접속되어 상기 수직동기신호와 의사수직동기신호를 스위칭출력하는 배타적 논리합게이트(102)와 그 배타적 논리합게이트(102)의 출력을 반전 처리하는 인터버(104)를 갖추어 구성된 것을 특징으로 하는 화상표시장치의 의사동기신호 생성회로.2. The switching unit (100) of the pseudo synchronous signal generating means (17) according to claim 1, wherein one end is connected to a vertical synchronous signal separated from the image signal and the other end is connected to the pseudo synchronously generated vertical synchronous signal. And an exclusive logic sum gate 102 for switching and outputting the vertical synchronizing signal and the pseudo vertical synchronizing signal, and an inverter 104 for inverting the output of the exclusive logic sum gate 102. Pseudo-synchronous signal generation circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950002728A 1995-02-15 1995-02-15 Pseudo-synchronous signal generation circuit of image display device KR0145914B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100584982B1 (en) * 2004-11-23 2006-05-29 삼성전기주식회사 Scan Synchronizer of Display System Using Spatial Light Modulator and Its Method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100584982B1 (en) * 2004-11-23 2006-05-29 삼성전기주식회사 Scan Synchronizer of Display System Using Spatial Light Modulator and Its Method

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