KR960030641A - Digital Noise Reduction Device Using Interpolation - Google Patents

Digital Noise Reduction Device Using Interpolation Download PDF

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Publication number
KR960030641A
KR960030641A KR1019950001776A KR19950001776A KR960030641A KR 960030641 A KR960030641 A KR 960030641A KR 1019950001776 A KR1019950001776 A KR 1019950001776A KR 19950001776 A KR19950001776 A KR 19950001776A KR 960030641 A KR960030641 A KR 960030641A
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South Korea
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output
latch
noise
difference
frame
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KR1019950001776A
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Korean (ko)
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KR100213024B1 (en
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서진교
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0135—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving interpolation processes

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)
  • Noise Elimination (AREA)

Abstract

연속되는 3개의 프레임간의 상관성을 이용하여 잡음저감처리를 행하는 디지탈 잡음저감장치가 개시된다.Disclosed is a digital noise reduction device that performs noise reduction processing using correlation between three consecutive frames.

본 발명에 따른 디지탈 잡음저감장치는 그에 입력되는 디지탈 영상신호를 1수평주기만큼 래치시켜 출력하는 제1래치; 상기 제1래치의 입력과 출력의 차를 검출하는 제1피일드간 차신호 검출기; 상기 제1래치의 출력을 1프레임주기만큼 지연시켜 출력하는 제1프레임메모리; 상기 제1래치의 입력과 상기 제1프레임 메모리의 출력의 차를 검출하는 제1프레임간 차신호 검출기; 상기 제1피일드간 차신호 검출기의 출력과 상기 제1프레임간 차신호 검출기의 출력에 근거하여 잡음의 유무를 판별하고, 잡음의 유무에 따라 보간값을 출력하는 제1잡음판별부; 상기 제1래치의 출력과 상기 제1잡음 판별부의 출력을 가산시켜 출력하는 제1가산부; 상기 제1가산부에서 출력되는 신호를 1수평주기만큼 래치시켜 출력하는 제2래치; 상기 제2래치의 입력과 출력의 차를 검출하는 제2피일드간 차신호 검출기; 상기 제2래치의 출력을 1프레임주기만큼 지연시켜 출력하는 제2프레임메모리; 상기 제2래치의 입력과 상기 제2프레임메모리의 출력의 차를 검출하는 제2프레임간 차신호 검출기; 상기 제2피일드간 차신호 검출기의 출력과 상기 제2프레임간 차신호 검출기의 력에 근거하여 잡음의 유무를 판별하고, 잡음의 유무에 따라 보간값을 출력하는 제2잡음판별부; 상기 제2래치의 출력과 상기 제2잡음판별부의 출력을 가산시켜 출력하는 제2가산부를 포함함을 특징으로 한다.A digital noise reduction device according to the present invention comprises: a first latch for latching and outputting a digital video signal input thereto by one horizontal period; A first signal difference detector detecting a difference between an input and an output of the first latch; A first frame memory for delaying and outputting the output of the first latch by one frame period; A first frame difference signal detector for detecting a difference between an input of the first latch and an output of the first frame memory; A first noise discriminating unit determining whether noise is present based on an output of the first feed difference signal detector and an output of the first inter frame difference signal detector, and outputting an interpolation value according to the presence or absence of noise; A first adder configured to add an output of the first latch and an output of the first noise discriminator to output the first latch; A second latch for latching and outputting the signal output from the first adder by one horizontal period; A second signal difference detector detecting a difference between an input and an output of the second latch; A second frame memory for delaying and outputting the output of the second latch by one frame period; A second frame difference signal detector for detecting a difference between an input of the second latch and an output of the second frame memory; A second noise discriminator configured to determine the presence or absence of noise based on the output of the difference signal detector between the second feed and the output of the difference signal detector between the second frames, and output an interpolation value according to the presence or absence of noise; And a second adder configured to add and output the output of the second latch and the output of the second noise discriminator.

본 발명에 따른 잡음저감장치는 연속되는 3개의 프레임을 사용하여 잡음의 유무를 판별하게 되므로 종래의 잡음저감장치에 비해 판단착오의 확율이 현저히 줄어들게 되는 효과를 갖는다.Since the noise reduction apparatus according to the present invention determines the presence or absence of noise by using three consecutive frames, the probability of judgment and error is significantly reduced compared to the conventional noise reduction apparatus.

Description

보간을 이용한 디지탈 잡음저감장치Digital Noise Reduction Device Using Interpolation

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 디지탈 잡음저감장치를 보이는 블럭도이다. 제2도는 제1도에 도시된 잡음판별부의 동작을 보이는 단면도이다. 제3도는 본 발명에 따른 디지탈 잡음저감장치를 보이는 블럭도이다.1 is a block diagram showing a conventional digital noise reduction device. 2 is a cross-sectional view showing the operation of the noise discriminator shown in FIG. 3 is a block diagram showing a digital noise reduction device according to the present invention.

Claims (1)

프레임내 혹은 프레임간의 상관성의 크기에 따라 잡음저감처리를 행하는 디지탈 잡음저감장치에 있어서, 그에 입력되는 디지탈 영상신호를 1수평주기만큼 래치시켜 출력하는 제1래치; 상기 제1래치의 입력과 출력의 차를 검출하는 제1피일드간 차신호 검출기; 상기 제1래치의 출력을 1프레임주기만큼 지연시켜 출력하는 제1프레임메모리; 상기 제1래치의 입력과 상기 제1프레임메모리의 출력의 차를 검출하는 제1프레임간 차신호 검출기; 상기 제1피일드간 차신호 검출기의 출력과 상기 제1프레임간 차신호 검출기의 출력에 근거하여 잡음의 유무를 판별하고. 잡음의 유무에 따라 보간값을 출력하는 제1잡음판별부; 상기 제1래치의 출력과 상기 제1잡음 판별부의 출력을 가산시켜 출력하는 제1가산부; 상기 제1가산부에서 출력되는 신호를 1수평주기만큼 래치시켜 출력하는 제2래치; 상기 제2래치의 입력과 출력의 차를 검출하는 제2피일드간 차신호 검출기; 상기 제2래치의 출력을 1프레임주기만큼 지연시켜 출력하는 제2프레임메모리; 상기 제2래치의 입력과 상기 제2프레임메모리의 출력의 차를 검출하는 제2프레임간 차신호 검출기; 상기 제2피일드간 차신호 검출기의 출력과 상기 제2프레임간 차신호 검출기의 출력에 근거하여 잡음의 유무를 판별하고, 잡음의 유무에 따라 보간값을 출력하는 제2잡음판별부; 상기 제2래치의 출력과 상기 제2잡음판별부의 출력을 가산시켜 출력하는 제2가산부를 포함하며 상기 제2가산부의 출력으로부터 잡음이 경감된 출력신호를 제공하는 디지탈 잡음경감장치.1. A digital noise reduction device for performing noise reduction processing according to the magnitude of correlation in a frame or between frames, comprising: a first latch for latching and outputting a digital video signal input thereto by one horizontal period; A first signal difference detector detecting a difference between an input and an output of the first latch; A first frame memory for delaying and outputting the output of the first latch by one frame period; A first frame difference signal detector for detecting a difference between an input of the first latch and an output of the first frame memory; Determining the presence or absence of noise based on the output of the first feed difference signal detector and the output of the first inter frame difference signal detector. A first noise discriminating unit outputting an interpolation value depending on the presence or absence of noise; A first adder configured to add an output of the first latch and an output of the first noise discriminator to output the first latch; A second latch for latching and outputting the signal output from the first adder by one horizontal period; A second signal difference detector detecting a difference between an input and an output of the second latch; A second frame memory for delaying and outputting the output of the second latch by one frame period; A second frame difference signal detector for detecting a difference between an input of the second latch and an output of the second frame memory; A second noise discriminating unit determining whether noise is present based on the output of the second signal between the second signal and the output of the signal between the second frame, and outputting an interpolation value according to the presence or absence of noise; And a second adder configured to add an output of the second latch and an output of the second noise discriminator, and to provide an output signal in which noise is reduced from the output of the second adder. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950001776A 1995-01-28 1995-01-28 Digital noise reduction device by using interpolation KR100213024B1 (en)

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KR1019950001776A KR100213024B1 (en) 1995-01-28 1995-01-28 Digital noise reduction device by using interpolation

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Application Number Priority Date Filing Date Title
KR1019950001776A KR100213024B1 (en) 1995-01-28 1995-01-28 Digital noise reduction device by using interpolation

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KR960030641A true KR960030641A (en) 1996-08-17
KR100213024B1 KR100213024B1 (en) 1999-08-02

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US7554611B2 (en) 2005-04-19 2009-06-30 Samsung Electronics Co., Ltd. Method and apparatus of bidirectional temporal noise reduction

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