KR960004133B1 - Video signal noise reduction circuit - Google Patents

Abstract

The noise in an image processing system is detected and reduced by using the correlations between the ingradient pixels and the upper and lower pixels. The circuit includes a first line memory(10) for delaying input video signal by 1H, a second line memory(20) for displaying output signal of the first line memory by 1H, a correlation detector(30) discriminating noise component in the video signal by detecting the correlations between the ingradient pixels and the upper and lower pixels, a lowpass filter(40) for filtering output signal of the first line memory(10), a subtracter(50) for calculating a high frequency components in output signal of the first line memory(10), a MUX(60) for selecting output signal of the subtracter(50) or zero level signal, and an adder(70) for adding output signals of the lowpass filter(40) and the MUX(60).

Description

Noise Reduction Circuit of Image Processing System

1 is a noise removing circuit diagram according to the present invention

2 is a detailed circuit diagram of the correlation detector 3 during the first period.

* Explanation of symbols for main parts of the drawings

10,20: first to second line memory 30: correlation detector

40: low pass filter 50: subtractor

60: MUX 70: Adder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise removing circuit in an image processing system. More particularly, the present invention relates to a noise removing circuit that discriminates and removes noise based on detection of correlation between gradient pixel components and vertical pixel components.

In general, a video signal generates noise that damages a signal due to a channel and an environment, thereby causing image quality. In addition, there are various kinds of noise generated in the television signal, among which the luminance is very high, and the pulse noise or the impulse noise has a great influence on the image quality deterioration. As described above, pulse noise and impulsive noise, which cause deterioration in image quality, are mostly high frequency components and there is no correlation between lines.

Accordingly, an object of the present invention is to provide a noise removing circuit capable of discriminating and removing noise in accordance with the correlation detection of the gradient pixel component and the vertical pixel component.

Another object of the present invention is to provide a noise removing circuit capable of removing noise without damaging the original signal.

Another object of the present invention is to provide a noise removing circuit for preventing deterioration of image quality.

According to an aspect of the present invention, there is provided a first line memory for inputting a video signal and outputting a 1H delayed video signal, and a second outputting 1H delayed video signal for outputting the 2H delayed video signal in the first line memory. A correlation detector which inputs a two-line memory, the video signal, a 1H delayed video signal, and a 2H delayed video signal to detect a correlation between the gradient pixel component and the vertical pixel component to generate a noise discrimination signal according to a predetermined threshold value; A low pass filter for low-pass filtering the 1H delayed video signal from the first line memory and a low pass filtered signal from the low pass filter 40 from the 1H delayed video signal of the first line memory are subtracted. An output subtractor and a high frequency component signal and a zero level signal outputted from the subtractor It characterized by configured to select the MUX output, a low-band component signal and a selection signal output from the MUX output from the low-pass filter in accordance with the specific signal to the adder for adding the output.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a noise cancellation circuit diagram according to the present invention, wherein a first line memory 10 for inputting an original video signal and outputting a video signal delayed by 1H and a video signal 1H delayed at the first line memory 10 are again 1H. A second line memory 20 which delays and outputs a 2H delayed video signal, and inputs the original video signal, a 1H delayed video signal, and a 2H delayed video signal to detect a correlation between the gradient pixel component and the vertical pixel component, A correlation detector 30 for generating a nod discrimination signal based on a threshold value, a low pass filter 40 for low-pass filtering the image signal delayed by 1H from the first line memory 10, and the first line memory; A subtractor 50 outputting a high pass component by subtracting the low pass filtered signal from the low pass filter 40 from the 1H delayed video signal of (10), and a high pass component output from the subtractor 50; A MUX 60 inputting a low level signal and selecting and outputting the low level component signal output from the low pass filter 40 and the MUX 60 selectively outputting the signal according to the noise discrimination signal of the correlation detector 30. The adder 70 adds and outputs a signal.

FIG. 2 is a detailed circuit diagram of the correlation detector 30 during the first period. The first pixel delay unit A1 and the first pixel delay unit for inputting the original image signal a1 and outputting the signal a2 delayed by one pixel are shown in FIG. A second pixel delayer A2 for outputting a two pixel delayed signal a3 by delaying the signal a2 delayed by one pixel again at A1 and one pixel by inputting the 2H delayed image signal b1; A third pixel delayer A3 for outputting the delayed signal b2, and a signal delayed by 2 pixels by inputting the signal b2 delayed by 1 pixel from the second pixel delayer A3 and delaying 1 pixel again. A first subtractor A5 for subtracting the second pixel delayed signal b3 of the fourth pixel delayer A4 from the fourth pixel delayer A4 and the original image signal a1, and A second subtractor A6 which subtracts the one pixel delayed signal b2 of the third pixel delayer A3 from the one pixel delayed signal a2 of the one pixel delayer A1, and A third subtractor A7 which subtracts the 2H delayed video signal b1 from the two pixel delayed signal a3 of the second pixel delayer A2, the original video signal a1 and the fourth pixel delayed signal; The first adder A8, which adds the two pixel delay signal b3 of (A4), the one pixel delay signal a2 of the first pixel delay unit A1, and one of the third pixel delay unit A3. A second adder A9 for adding the pixel delay signal b2 and a third adder for adding the 2H delayed video signal b1 and the two pixel delay signal a3 of the second pixel delayer A2 ( A first absolute value A11 which takes an absolute value of A10 and the signals subtracted from the first subtractor A5 and outputs the absolute value, and a signal a2-b2 subtracted from the second subtractor A6. ) Is a second absolute value (A12) for taking an absolute value and outputting, a third absolute value (A13) for taking an absolute value and outputting the signal (a3-b1) subtracted from the third subtractor (A7), and Absolute value in the first absolute stroke A11 A fifth pixel delayer A14 for inputting the taken signal and outputting a signal delayed by one pixel and a fifth pixel delayer A14 add a signal obtained by taking the absolute value of the first pixel and the first absolute stroke A1 in the fifth pixel delayer A14. A first priority encoder A20 for inputting a fourth adder A17 and a signal added by the fourth adder A17 to encode and output the signal based on the priority, and A sixth pixel delay unit A15 for outputting a signal delayed by one pixel by inputting a signal having an absolute value in the second absolute stroke A12, and a one pixel delay signal and the first signal in the sixth pixel delay unit A15; A second adder A18 that adds a signal obtained by taking the absolute value of the absolute value A12 and a signal added by the fifth adder A18 are input so that the magnitude of the signal can be encoded in a priority order. A second priority encoder A21 for outputting; A seventh pixel delayer A16 for inputting a signal having an absolute value in the substitution A13 and outputting a one pixel delayed signal; and a one pixel delayed signal and the third absolute signal in the seventh pixel delayer A16. A sixth adder (A19) for adding a signal obtained by taking the absolute value of the stroke (A13) and a signal added in the sixth adder (A19) are input to encode and output the signal size in order to determine the priority. A first minimum value detector A23 for detecting a small value by inputting a third priority encoder A22, an output value of the first-second priority encoders A20-A21, and the second-3; Fourth and fifth priority encoders A25 and A26 which respectively input and output the output values of the priority encoders A21 and A22 so as to determine the magnitude of the small signal, and the fourth and fifth priority. Detecting a minimum value by inputting encoding values of encoders A25-A26 respectively (A27), a 1½ amplifier A28 which ½ amplifies and outputs the signal a1 + b1 added by the first adder A8, and a signal a2 + b2 added by the second adder A9. A 2½ amplifier (A29) outputting ½ amplification, a 3½ amplifier (A30) ½ amplifying outputting the signal (a3 + b1) added by the third adder (A10), and the first-third amplifier ( MUX (A31) for inputting the output signal of a28-a30 respectively and selectively outputting by the output signal of the third minimum value detector (a27), and delaying the 1H delayed image signal by one pixel to generate a path generated over a processing point or more. A fourth subtractor for subtracting the compensated signal delayed by one pixel from the eighth pixel delayer A34 from the eighth pixel delayer A34 for compensating for the delay and outputting the selected signal from the MUX A31 ( A32), a fourth absolute value A33 for inputting the subtracted output signal of the fourth subtractor A32, taking an absolute value and outputting it, and the fourth The comparator A35 compares a signal obtained with the absolute value of the absolute value A23 with a predetermined threshold value and outputs a noise discrimination signal.

Based on the above-described configuration, an embodiment of the present invention will be described in detail with reference to FIGS.

The first line memory 10 which inputs the original video signal a1 outputs a 1h delayed signal b1. The second line memory 20 inputting the 1H delay signal b1 of the first line memory 10 outputs the 2H delayed signal cl by delaying 1H. The low pass filter 40, which inputs the 1H delay signal b1 from the first line memory 10, performs low pass filtering. At this time, the subtractor 50 subtracts and outputs the low pass signal filtered by the low pass filter 40 from the 1H delayed signal b1 of the first line memory 10.

In addition, the correlation detector 30 for inputting the original video signal a1, the 1H delayed video signal b1, and the 2H delayed video signal cl detects the correlation between the lines, and compares the predetermined value with a threshold value of " 0 ". When outputting the signal, it is determined that it is a high-frequency signal, and when outputting "1", it is determined as noise. Therefore, when the output of the correlation detector 30 is "0", it is determined as a normal signal, and the MUX 60 selectively outputs the high frequency component signal output from the subtractor 50. The high pass signal output from the MUX 60 and the low pass signal filtered by the low pass filter 40 are added and output by the adder 70. However, when the output of the correlation detector 30 is "1". The MUX 60 selects and outputs a zero level determined by the noise, and the adder 70 outputs only the low pass signal output from the low pass filter 40.

The detailed operation of the correlation detector 30 will be described with reference to FIG. 2. The correlation of neighboring pixels with respect to the pixel currently being processed to detect noise, and the most highly correlated pixels with the processing pixel will be described. The absolute value of the difference determines whether the processing pixel is noisy. That is, when the original video signal a1 is input through the input terminal P1, the first pixel delay unit A1 outputs the video signal a2 delayed by one pixel. The second pixel delayer A2, which inputs the video signal a2 delayed by one pixel from the first pixel delayer A1, delays the first pixel by one pixel to delay the two pixel delayed video signal a3 from the first subtracter A7. Output to the third adder A10. When the video signal b1 delayed by 1H is input through the input terminal P2, the third pixel delay unit A3 outputs the video signal b2 delayed by one pixel. The fourth pixel delayer A4, which inputs the video signal b2 delayed by one pixel from the third pixel delayer A3, converts the video signal b3 delayed by two pixels into a first subtractor A1 and a first adder ( Output to A8).

As a result, the first subtractor A5 outputs an image signal b3 delayed by two pixels of the fourth pixel retarder A4 from the original image signal a1. The second subtractor A6 subtracts the one pixel delayed image signal b2 of the third pixel delayer A3 from the first pixel delayed image signal a2. The third decelerator A7 subtracts the 1H delay operation signal b1 input through the input terminal P2 from the two pixel delay signal a3 of the second pixel delayer A2. The first absolute value A11 for inputting the subtraction signals a1-b3 of the first subtractor A5 takes an absolute value and outputs the absolute value. The signal which takes the absolute value in the first absolute value A11 is delayed by one pixel in the fifth pixel delayer A14, and the output value of the first absolute value A11 which is not delayed is added by the fourth adder A17. do. The signal added by the fourth adder A17 is input to the first priority encoder A20 to be encoded and output so that the magnitude of the signal can be compared. The second absolute value A12 for inputting the subtraction signals a2-b2 of the second subtraction A6 takes an absolute value and outputs the absolute value. The signal obtained by taking the absolute value from the second absolute value A12 is delayed by one pixel in the sixth pixel delayer A16, and is added by the fifth adder A18 and the output value of the second non-delayed absolute value A12. . The signal added by the fifth adder A18 is input to the second priority encoder A21 and encoded and output so that the magnitude of the signal can be compared. The third absolute value A13, which inputs the third subtractor A7 subtraction signal a3-b1, takes an absolute value and outputs it. The absolute value of the signal obtained by the third absolute value A13 is delayed by one pixel in the seventh pixel delayer A16, and the output value of the non-delayed third absolute value A is added by the sixth adder A19. do. The signal added by the sixth adder A19 is input to the third priority encoder A22 to encode and output the signal so that the magnitude of the signal can be compared. A first minimum value detector A23 for inputting the encoding output values of the first and second priority encoders A20-A21_ detects and outputs a minimum value.

The second minimum value detector A24 which inputs the encoding output value of the second-priority encoder A24 detects and outputs the minimum value. A fourth priority encoder A25 that inputs the minimum value output from the first minimum value detector A23 encodes and outputs the signal to be compared with each other. A fifth priority encoder A26 that inputs the minimum value output from the second minimum value detector A24 encodes and outputs the signal to be compared with each other.

The third minimum value detector A27 which inputs the output signals of the fourth through fifth priority encoders A25 and A26 respectively detects the minimum value of the two signals and outputs the minimum value of the two signals to the selection terminal S of the MUX A31.

On the other hand, the signal added and output from the first-third adder (A8-A10) is first-first. Each level in the amplifier (A28-A30) Amplified Each signal is output. The first-first Amplifier (A28-A30) output The MUX A31 inputting the signal is selected by the output signal of the third minimum value detector A27 and output to the fourth subtractor A32. At this time, when the 2H delayed image c1 is inputted through the input terminal P3 in the second line memory 20, the pixel is delayed by one pixel from the eighth pixel delayer A34 to be the fourth subtractor A32. The one pixel delayed signal in the eighth pixel delayer A34 becomes a processing pixel. The fourth subtraction A32 subtracts the processing pixel signal of the eighth pixel delay unit A34 from the signal output by the MUX A31.

The signal subtracted by the subtractor A32 takes an absolute value at the fourth absolute stroke A33. The comparator A35 for inputting a signal having an absolute value at the fourth absolute stroke A33 determines a noise signal by comparing a predetermined threshold input through the input terminal P4, and outputs the comparator A35. If "1" is noise, "0" is frequency signal.

That is, the correlation is checked by pairing (a1-b3) (a2-b2) (a3-b1) among processing pixels in the window. In this case, the correlation is determined as an absolute value of an operation value, in which the previous pixel correlation is added to the correlation of the current pixel pair in the same direction to further absorb the amount of information in the horizontal direction in the window fixed at 3x3. The degree of correlation with respect to the direction is determined.

As described above, the noise is a high frequency component, and by using the property that there is no correlation between the lines, noise is determined by removing the noise according to the correlation detection on the gradient pixel component, thereby providing a clear image quality.

Claims (2)

In the noise removing circuit of the image processing system, a first line memory 10 for inputting a video signal and outputting a video signal delayed by 1H and a video signal delayed by 1H in the first line memory 10 are delayed again by 1H. The second line memory 20 which outputs the delayed video signal, the video signal, the 1H delayed video signal, and the 2H delayed video signal are input to detect the correlation between the gradient pixel component and the up and down pixel component, and according to a predetermined threshold value. A correlation detector 30 generating a noise discrimination signal, a low pass filter 40 for low-pass filtering the image signal delayed by 1H from the first line memory 10, and a 1H of the first line memory 10. A subtractor 50 outputting a high frequency component by subtracting the signal filtered by the low pass filter 40 from the delayed video signal, and a high frequency component signal and a zero level signal output from the subtractor 50 are inputted. An adder for adding and outputting the MUX 60 to be selectively output according to the noise discrimination signal of the correlation detector 30, the low pass component signal output from the low pass filter 40 and the signal selected and output from the MUX 60 ( 70) a noise canceling circuit comprising: a. The noise canceling circuit of claim 1, wherein the correlation detector (30) determines whether noise is detected by detecting a correlation between lines by giving priority to a pair of upper and lower pixels and an inclined pixel.