KR960027881A - SSCOP (Service Specific Connection Oriented Protocol) Processing Circuit - Google Patents

SSCOP (Service Specific Connection Oriented Protocol) Processing Circuit Download PDF

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Publication number
KR960027881A
KR960027881A KR1019940038189A KR19940038189A KR960027881A KR 960027881 A KR960027881 A KR 960027881A KR 1019940038189 A KR1019940038189 A KR 1019940038189A KR 19940038189 A KR19940038189 A KR 19940038189A KR 960027881 A KR960027881 A KR 960027881A
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KR
South Korea
Prior art keywords
fifo
sscop
reception
state
message
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Application number
KR1019940038189A
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Korean (ko)
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KR0140679B1 (en
Inventor
윤성욱
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배순훈
대우전자 주식회사
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Priority to KR1019940038189A priority Critical patent/KR0140679B1/en
Publication of KR960027881A publication Critical patent/KR960027881A/en
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Publication of KR0140679B1 publication Critical patent/KR0140679B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/28—Timers or timing mechanisms used in protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5629—Admission control
    • H04L2012/563—Signalling, e.g. protocols, reference model
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H04L2012/5653—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

본 발명은 비동기 전달모드(ATM:Asynchronous Transfer Mode)통신방식을 기본전달수단으로 하는 B-ISDN에서 사용하는 신호프로토콜 중 SSCOP(Service Specific Connection Oriented Protocol)을 구현하는 회로에 관한 것으로, 전체회로의 상태 및 상태변수를 저장하고 상위계층 또는 수신된 메세지로부터 각종신호를 인가받아 상태를 조절하고 그에 따른 각종 제어신호 및 에러 신호를 출력하도록 된 상태제어부(10); 상기 상태 제어부(10)의 제어신호에 의해 소정의 시간정보를 출력하도록 된 타이머(20); 상기 상태제어부(10)의 제어신호에 의해 SSCOP FIFO(30)에 저장된 상위계층으로부터 전달된 데이타를 입력받아 소정길이의 패드 및 제어 필드를 부가하여 AAL FIFO(100)로 출력하게 된 PDU 전송부(40); 수신 AAL FIFO(102)에 저장된 수신메세지를 읽어서 저장한 뒤 SSCOP FIFO(52)로 출력하게 된 수신 큐 FIFO(50); 상기 수신 FIFO(50)에 입력되는 메세지를 해석하여 PDU 타입 내지 각종 상태변수를 상기 상태제어부(10)에 입력하게 된 PDU 해석부(60) 및; 상기 상태제어부(10)의 제어신호에 의해 전체회로를 초기화시키는 CPU(70)로 구성된 것이다.The present invention relates to a circuit that implements SSCOP (Service Specific Connection Oriented Protocol) among the signal protocols used in B-ISDN, which is based on Asynchronous Transfer Mode (ATM) communication. And a state control unit 10 configured to store state variables, adjust various states by receiving various signals from higher layers or received messages, and output various control signals and error signals accordingly. A timer 20 configured to output predetermined time information according to the control signal of the state controller 10; PDU transmission unit for receiving the data transmitted from the upper layer stored in the SSCOP FIFO (30) by the control signal of the state control unit 10 to add a pad and a control field of a predetermined length to output to the AAL FIFO (100) 40); A reception queue FIFO 50 for reading and storing a reception message stored in the reception AAL FIFO 102 and outputting the received message to the SSCOP FIFO 52; A PDU analyzer 60 for interpreting a message input to the reception FIFO 50 and inputting a PDU type or various state variables to the state controller 10; It is composed of a CPU 70 for initializing the entire circuit by the control signal of the state control unit 10.

Description

SSCOP(Service Specific Connection Oriented Protocol) 처리회로SSCOP (Service Specific Connection Oriented Protocol) Processing Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 따른 SSCOP 처리회로를 도시한 구성블럭도, 제5도는 본 발명에 따른 SSCOP 처리회로에서 SSCOP FIFO로부터 송신 큐 FIFO로 전송시 길이신호에 따른 처리회로를 도시한 도면, 제6도는 본 발명에 따른 SSCOP 처리회로에서 수신 AAL FIFO로부터 수신 큐 FIFO로 전송시 길이신호에 따른 처리회로를 도시한 도면이다.FIG. 4 is a block diagram showing an SSCOP processing circuit according to the present invention. FIG. 5 is a view showing a processing circuit according to a length signal when transmitting from the SSCOP FIFO to the transmission queue FIFO in the SSCOP processing circuit according to the present invention. FIG. 4 is a diagram illustrating a processing circuit according to a length signal when transmitting from a receiving AAL FIFO to a receiving queue FIFO in the SSCOP processing circuit according to the present invention.

Claims (2)

전체회로의 상태 및 상태변수를 저장하고 상위계층 또는 수신된 메세지로부터 각종신호를 인가받아 상태를 조절하고 그에 따른 각종 제어신호 및 에러 신호를 출력하도록 된 상태제어부(10); 상기 상태제어부(10)의 제어신호에 의해 소정의 시간정보를 출력하도록 된 타이머(20); 상기 상태제어부(10)의 제어신호에 의해 SSCOP FIFO(30)에 저장된 상위계층으로부터 전달된 데이타를 입력받아 소정길이의 패드 및 제어필드를 부가하여 AAL FIFO(100)로 출력하게 된 PDU 전송부(40); 수신 AAL FIFO(102)에 저장된 수신메세지를 읽어서 저장한 뒤 SSCOP FIFO(52)로 출력하게 된 수신 큐 FIFO(50); 상기 수신큐 FIFO(50)에 입력되는 메세지를 해석하여 PDU 타입 내지 각종 상태변수를 상기 상태제어부(10)에 입력하게 된 PDU 해석부(60) 및; 상기 상태제어부(10)의 제어신호에 의해 전체회로를 초기화시키는 CPU(70)로 구성된 SSCOP 처리회로.A state controller 10 for storing the state and state variables of the entire circuit, adjusting the state by receiving various signals from a higher layer or a received message, and outputting various control signals and error signals accordingly; A timer 20 configured to output predetermined time information according to the control signal of the state controller 10; PDU transmission unit for receiving the data transmitted from the upper layer stored in the SSCOP FIFO (30) by the control signal of the state control unit 10 to add a pad and a control field of a predetermined length to output to the AAL FIFO (100) 40); A reception queue FIFO 50 for reading and storing a reception message stored in the reception AAL FIFO 102 and outputting the received message to the SSCOP FIFO 52; A PDU analyzer 60 for interpreting a message input to the reception queue FIFO 50 and inputting a PDU type or various state variables to the state controller 10; SSCOP processing circuit comprising a CPU (70) for initializing the entire circuit by the control signal of the state control unit (10). 제1항에 있어서, 상기 SSCOP FIFO(30)에 저장된 데이타에 길이정보를 부가하여 저장하게 된 전송 큐 FIFO(32)와, 상기 전송 큐 FIFO(32)에 저장된 데이타를 소정의 순서번호에 의해 관리하다가 전송 중 손실된 데이타만 재전송 큐 FIFO(34)를 통해 상기 PDU 전송부(40)로 출력하여 재전송할 수 있게 된 전송버퍼(36)로 구성된 재전송수단과; 상기 수신 큐 FIFO(50)에 저장된 수신메세지에 길이정보를 부가하여 저장하다 결손된 메세지를 보충하여 상기 수신 SSCOP FIFO(52)에 출력하게 된 수신 큐 버퍼(54)가 추가로 구성된 것을 특징으로 하는 SSCOP 처리회로.The transmission queue FIFO 32, which stores length information added to data stored in the SSCOP FIFO 30, and manages data stored in the transmission queue FIFO 32 by a predetermined sequence number. A retransmission means composed of a transmission buffer 36 capable of retransmitting only data lost during transmission to the PDU transmitter 40 through a retransmission queue FIFO 34; The reception queue buffer 54 is configured to add length information to the reception message stored in the reception queue FIFO 50 and to compensate for the missing message and output the received message to the reception SSCOP FIFO 52. SSCOP processing circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940038189A 1994-12-28 1994-12-28 Circuit for processing sscop KR0140679B1 (en)

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KR960027881A true KR960027881A (en) 1996-07-22
KR0140679B1 KR0140679B1 (en) 1998-07-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100679820B1 (en) * 2005-09-06 2007-02-06 엘지전자 주식회사 Method for scheduling data packet retransmission on wireless communication network

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100679820B1 (en) * 2005-09-06 2007-02-06 엘지전자 주식회사 Method for scheduling data packet retransmission on wireless communication network

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