KR960027862A - How to improve error of analog / digital converter - Google Patents

How to improve error of analog / digital converter Download PDF

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Publication number
KR960027862A
KR960027862A KR1019940035469A KR19940035469A KR960027862A KR 960027862 A KR960027862 A KR 960027862A KR 1019940035469 A KR1019940035469 A KR 1019940035469A KR 19940035469 A KR19940035469 A KR 19940035469A KR 960027862 A KR960027862 A KR 960027862A
Authority
KR
South Korea
Prior art keywords
analog
digital converter
sample
input terminal
hold circuit
Prior art date
Application number
KR1019940035469A
Other languages
Korean (ko)
Other versions
KR0138870B1 (en
Inventor
이병민
양기곤
Original Assignee
양승택
재단법인 한국전자통신연구소
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 양승택, 재단법인 한국전자통신연구소 filed Critical 양승택
Priority to KR1019940035469A priority Critical patent/KR0138870B1/en
Publication of KR960027862A publication Critical patent/KR960027862A/en
Application granted granted Critical
Publication of KR0138870B1 publication Critical patent/KR0138870B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
    • H03M1/181—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values
    • H03M1/183—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

본 발명은 아날로그/디지탈 변환기의 오차 개선 방법에 관한 것이다. 본 발명은 아날로그/디지탈 변환기의 입력단에 샘플앤홀드 회로을 부가하고 상기 샘플앤홀드 회로를 통하여 아날로그 신호를 입력하므로써, 아날로그/디지탈 변환기가 변환하는 동안 그 입력단의 신호를 일정하게 유지하는 과정으로 수행되는 것을 특징으로 하여, 아날로그/디지탈 변환기의 출력의 오차를 개선할 수 있는 효과가 있다.The present invention relates to a method for improving the error of an analog / digital converter. The present invention is performed by adding a sample and hold circuit to an input terminal of an analog / digital converter and inputting an analog signal through the sample and hold circuit, thereby maintaining a constant signal at the input terminal during the conversion of the analog / digital converter. It is characterized in that the error of the output of the analog-to-digital converter can be improved.

Description

아날로그/디지탈 변환기의 오차 개선 방법How to improve error of analog / digital converter

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명이 적용되는 순차근사형 아날로그/디지탈 변환기의 회로도.1 is a circuit diagram of a sequential approximation analog / digital converter to which the present invention is applied.

Claims (1)

아날로그/디지탈 변환기의 입력단에 샘플앤홀드 회로(30)을 부가하고 상기 샘플앤홀드 회로(30)를 통하여 아날로그 신호를 입력하므로써, 아날로그/디지탈 변환기가 변환하는 동안 그 입력단의 신호를 일정하게 유지하는 과정으로 수행되는 것을 특징으로 하는 아날로그/디지탈 변환기의 오차 개선 방법.By adding a sample and hold circuit 30 to the input terminal of the analog / digital converter and inputting an analog signal through the sample and hold circuit 30, the analog / digital converter keeps the signal at the input terminal constant during conversion. Error correction method of the analog / digital converter, characterized in that performed in the process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940035469A 1994-12-21 1994-12-21 Device for reducing the error of a/d converter KR0138870B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940035469A KR0138870B1 (en) 1994-12-21 1994-12-21 Device for reducing the error of a/d converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940035469A KR0138870B1 (en) 1994-12-21 1994-12-21 Device for reducing the error of a/d converter

Publications (2)

Publication Number Publication Date
KR960027862A true KR960027862A (en) 1996-07-22
KR0138870B1 KR0138870B1 (en) 1998-07-01

Family

ID=19402546

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940035469A KR0138870B1 (en) 1994-12-21 1994-12-21 Device for reducing the error of a/d converter

Country Status (1)

Country Link
KR (1) KR0138870B1 (en)

Also Published As

Publication number Publication date
KR0138870B1 (en) 1998-07-01

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