KR960027565A

KR960027565A - Longest Code Sequence Generator in Multichannel Wireless Communication Devices

Info

Publication number: KR960027565A
Application number: KR1019940038684A
Authority: KR
Inventors: 이희태
Original assignee: 정장호; Lg 정보통신주식회사
Priority date: 1994-12-29
Filing date: 1994-12-29
Publication date: 1996-07-22
Also published as: KR0141385B1

Abstract

본 발명은 다채널 무선통신 장치에서의 최장 부호열 발생기에 관한 것이다.The present invention relates to a longest code string generator in a multichannel wireless communication device.

종래의 최대 부호열 발생방식에서는 N-1개의 부호열 중에서 몇개를 선택하여 사용하기 위해서는 멀티플렉서를 구비해야하므로, 부호열의 길이가 긴 경우 N-1개의 부호중의 한개를 선택하는 회로를 구성하는데에 있어 어려움이 있었다. 이러한문제에 기인하여 실제 회로 구성상에 있어서는 여러개의 최장 부호열 발생기를 사용하는 것이 더 용이한 경우가 발생한다. 이와 같이 여러개의 최장 부호열 발생기를 사용하는 경우 하드웨어 구성이 매우 복잡하게 되는 문제점이 있다.In the conventional maximum code string generation method, a multiplexer must be provided in order to select and use several of the N-1 code strings. There was a difficulty. Due to this problem, it is often easier to use several longest code string generators in an actual circuit configuration. As described above, when a plurality of longest code string generators are used, a hardware configuration is very complicated.

본 발명은 간단한 회로 구성으로 최장 부호열을 효과적으로 발생할 수 있으므로, 다채널 무선통신 장치에 유용하게 적용할 수 있다.The present invention can effectively generate the longest code string with a simple circuit configuration, and thus can be usefully applied to a multi-channel wireless communication device.

Description

Longest Code Sequence Generator in Multichannel Wireless Communication Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 따른 다채널 무선통신 장치에서의 최장 부호열 발생기 구성도.4 is a configuration diagram of the longest code string generator in a multi-channel wireless communication device according to the present invention.

Claims

In the longest code string generator in a multi-channel wireless communication device, a latch 20 for storing code numbers received from a CPU, a data input terminal and an output terminal are interconnected, clocks at a clock input terminal, counter signals and preset signals at a clock input terminal. The first D flip-flop 20 outputs a signal generated by operating in accordance with the chip selection signal of the stage, and outputs the code number applied from the latch 20 according to the signal from the first D flip-flop 20. And a second D flip which outputs a signal generated by operating a plurality of AND gates 30, a data input terminal and an output terminal and operating according to a clock signal of a clock stage, a clear signal of a clear stage, and a code generation start signal of a preset stage. Inverter 80 for inverting the signal applied from the flop 50, the second D flip-flop 50, the clock applied to the clock terminal code number applied from the AND gate 30 and the inverter 80 Down counter 70 for outputting the count signal generated by counting down according to the signal applied to the enable stage, the data input stage and the output stage are interconnected, and the clock stage clock, preset stage count signal and clear stage A third D flip-flop 60 for outputting a signal generated by operating according to the chip select signal, and an OR for ORing the chip select signal and the count signal to a clear end of the second D flip-flop 50 as a clear signal An AND gate 100 for performing an AND operation on a gate 90, a signal applied to the first input terminal from the third D flip-flop 60, and a clock applied to the second input terminal, and an AND gate 100 applied to the gate 90. And a shift register section (110) for delaying and outputting a predetermined longest code string in accordance with a signal.

※ Note: The disclosure is based on the initial application.