KR960026421A - Manufacturing method of self-aligned heterojunction bipolar transistor - Google Patents
Manufacturing method of self-aligned heterojunction bipolar transistor Download PDFInfo
- Publication number
- KR960026421A KR960026421A KR1019940036377A KR19940036377A KR960026421A KR 960026421 A KR960026421 A KR 960026421A KR 1019940036377 A KR1019940036377 A KR 1019940036377A KR 19940036377 A KR19940036377 A KR 19940036377A KR 960026421 A KR960026421 A KR 960026421A
- Authority
- KR
- South Korea
- Prior art keywords
- emitter
- bipolar transistor
- film
- base
- self
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 239000004642 Polyimide Substances 0.000 claims abstract 3
- 229920001721 polyimide Polymers 0.000 claims abstract 3
- 150000001875 compounds Chemical class 0.000 claims abstract 2
- 238000005468 ion implantation Methods 0.000 claims abstract 2
- 239000004065 semiconductor Substances 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims 4
- 239000000758 substrate Substances 0.000 claims 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 238000001312 dry etching Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000000992 sputter etching Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02395—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
Abstract
본 발명에서는 화합물 반도체를 이용한 이종접합 바이폴라 트랜지스터의 제조시에 베이스-컬렉터 용량을 줄임으로써 최대 공진주파수를 향상시키기 위해 기존에 사용되던 이오주입시의 문제를 완화시킬 목적으로 에미터 영역 주위를 폴리이미드를 비롯한 이중의 측벽막에 의해 보호함으로써 베이스 오믹접촉 특성과 누설전류 발생을 개신시키며, 아울러 고속특성의 향상을 위해 에미터와 베이스의 자기정렬이 가능하도록 고안하였다.In the present invention, the polyimide around the emitter region for the purpose of alleviating the problem of the conventional ion implantation to improve the maximum resonance frequency by reducing the base-collector capacity in the production of heterojunction bipolar transistor using a compound semiconductor. It protects the base ohmic contact characteristics and leakage current by protecting it with a double sidewall film, and it is designed to enable self-alignment of emitter and base to improve high speed characteristics.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도의 (A)∼(F)는 본 발명의 제조공정을 나타낸 단면도.(A)-(F) is sectional drawing which showed the manufacturing process of this invention.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940036377A KR0148036B1 (en) | 1994-12-23 | 1994-12-23 | Method for manufacturing bipolar transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940036377A KR0148036B1 (en) | 1994-12-23 | 1994-12-23 | Method for manufacturing bipolar transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960026421A true KR960026421A (en) | 1996-07-22 |
KR0148036B1 KR0148036B1 (en) | 1998-11-02 |
Family
ID=19403219
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940036377A KR0148036B1 (en) | 1994-12-23 | 1994-12-23 | Method for manufacturing bipolar transistor |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0148036B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020031722A (en) * | 2000-10-23 | 2002-05-03 | 김우진 | Structure and method for heterojunction bipola transistor |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100491089B1 (en) * | 2002-12-06 | 2005-05-24 | 한국전자통신연구원 | Heterojunction bipolar transistor and manufacturing method thereof |
-
1994
- 1994-12-23 KR KR1019940036377A patent/KR0148036B1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020031722A (en) * | 2000-10-23 | 2002-05-03 | 김우진 | Structure and method for heterojunction bipola transistor |
Also Published As
Publication number | Publication date |
---|---|
KR0148036B1 (en) | 1998-11-02 |
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GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20030430 Year of fee payment: 6 |
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LAPS | Lapse due to unpaid annual fee |