KR960025580A - Image memory controller - Google Patents

Abstract

The present invention relates to an image memory control apparatus, and in particular, a first selector for alternately multiplexing first and second selection signals in response to a first clock signal; A second selector alternately multiplexing read and write address signals in response to the first clock signal; a first write or read data in response to the write control signal, the output signal of the first selector and the output signal of the second selector And second image memories; Transferring data of the second and third data buses to the first and second image memories in response to the first clock signal, or transferring data read from the first and second image memories to the second and third data buses; First and second bidirectional transmission gates; First latch means for latching data on the second data bus in response to the second clock signal and delaying the latched data to the fourth data bus; Second latch means for latching data on the third data bus and outputting the data to the fourth data bus in response to the second clock signal and the third clock signal; And an output transfer gate for transferring data of the fourth data bus.

Therefore, the present invention can write image data into the field memory during the screen refresh operation, thereby enabling high speed operation.

Description

Image memory controller

Since this is an open matter, no full text was included.

1 is a block diagram of an image memory control apparatus according to the present invention, and FIG. 2 is a waveform diagram of each part for explaining the operation of the first image memory control apparatus.

Claims (1)

A first selector for alternately multiplexing the first selection signal and the second selection signal in response to the first clock signal; A second selector for alternately multiplexing a read address signal and a write address signal in response to the first clock signal; A pair of first and second image memories for writing or reading data in response to a write control signal, an output signal of the first selector and an output signal of the second selector; First and second data transfer gates for transferring data of a first data bus to second and third data buses in response to the first clock signal; In response to the first clock signal, data of second and third data buses may be transferred to the first and second image memories or data read from first and second image memories may be transferred to the second and third data buses. First and second bidirectional transmission gates transmitting to the first and second bidirectional transmission gates; First latch means for latching data on the second data bus in response to a second clock signal and delaying the latched data to the fourth data bus by a half clock delay; Second latch means for outputting data on the third data bus and outputting the data on the third data bus in response to a second clock signal and a third clock signal; And an output transfer gate for transferring data of the fourth data bus. ※ Note: The disclosure is based on the initial application.